AT32F425
Series Reference Manual
2022.03.30
Page 108
Ver 2.01
Bit 12
GF4
0x0
ro
Channel 4 global event flag
0: No transfer error, half transfer or transfer complete event
occurred.
1: Transfer error, half transfer or transfer complete event
Bit 11
DTERRF3
0x0
ro
Channel 3 data transfer error event flag
0: No transfer error occurred.
1: Transfer error occurred.
Bit 10
HDTF3
0x0
ro
Channel 3 half transfer event flag
0: No half-transfer event occurred.
1: Half-transfer event occurred.
Bit 9
FDTF3
0x0
ro
Channel 3 transfer complete event flag
0: No transfer complete event occurred.
1: Transfer complete event occurred.
Bit 8
GF3
0x0
ro
Channel 3 global event flag
0: No transfer error, half transfer or transfer complete event
occurred.
1: Transfer error, half transfer or transfer complete event
Bit 7
DTERRF2
0x0
ro
Channel 2 data transfer error event flag
0: No transfer error occurred.
1: Transfer error occurred.
Bit 6
HDTF2
0x0
ro
Channel 2 half transfer event flag
0: No half-transfer event occurred.
1: Half-transfer event occurred.
Bit 5
FDTF2
0x0
ro
Channel 2 transfer complete event flag
0: No transfer complete event occurred.
1: Transfer complete event occurred.
Bit 4
GF2
0x0
ro
Channel 2 global event flag
0: No transfer error, half transfer or transfer complete event
occurred.
1: Transfer error, half transfer or transfer complete event
Bit 3
DTERRF1
0x0
ro
Channel 1 data transfer error event flag
0: No transfer error occurred.
1: Transfer error occurred.
Bit 2
HDTF1
0x0
ro
Channel 1 half transfer event flag
0: No half-transfer event occurred.
1: Half-transfer event occurred.
Bit 1
FDTF1
0x0
ro
Channel 1 transfer complete event flag
0: No transfer complete event occurred.
1: Transfer complete event occurred.
Bit 0
GF1
0x0
ro
Channel 1 global event flag
0: No transfer error, half transfer or transfer complete event
occurred.
1: Transfer error, half transfer or transfer complete event
9.4.2
DMA interrupt flag clear register (DMA_CLR)
Access: 0 wait state, accessible by bytes, half-words or words.
Bit
Register
Reset value
Type
Description
31: 28
Reserved
0x0
resd
Kept at its default value.
Bit 27
DTERRFC7
0x0
rw1c
Channel 7 data transfer error flag clear
0: No effect
1: Clear the DTERRF flag in the DMA_STS register
Bit 26
HDTFC7
0x0
rw1c
Channel 7 half transfer flag clear
0: No effect
1: Clear the HDTF7 flag in the DMA_STS register