AT32F425
Series Reference Manual
2022.03.30
Page 51
Ver 2.01
4.1.4
Clock fail detector
The clock fail detector (CFD) is designed to respond to HEXT clock failure when the HEXT is used as a
system clock ,directly or indirectly. If a failure is detected on the HEXT clock, a clock failure event is sent
to the break input of TMR1 and an interrupt is generated. This interrrpt is directly linked to CPU NMI so
that the software can perform rescue operations. The NMI interrupt keeps executing until the CFD
interrupt pending bit is cleared. This is why the CFD interrupt has to be cleared in the NMI service rounte.
The HEXT clock failure will result in a switch of the system clock to the HICK clock, the CFD to be
disabled , HEXT clock to be stopped, and even PLL to be disabled if the HEXT clock is selected as the
system clock through PLL.
4.1.5
Clock output
The microcontroller allows the internal clock signal to be output to external CLKOUT pins. That is,
ADCCLK, USB48M, SCLK, LICK, LEXT, HICK, HEXT, PLLCLK/2 can be used as CLKOUT clocks. When
being used as the CLKOUT clock output pin, the corresponding GPIO port registers must be configured
accordingly.
4.1.6
Interrupts
The microcontroller specifies a stable flag for each clock source. As a result, when a clock source is
enabled, it is possible to determine if the clock is stable by checking the flag pertaining to the clock
source. An interrupt request is generated when the interrupt corresponding to the clock source is enabled.
If a failure is detected on the HEXT clock, the CFD interrupt is generated. Such interrrpt is directly linked
to CPU NMI.
4.2 Reset
4.2.1
System reset
AT32F425 series provide the following system reset sources:
NRST reset: on the external NRST pin
WDT reset: watchdog overflow
WWDT reset: window watchdog overflow
CPU software reset: Cortex™-M4 software reset
Low-power management reset: This type of reset is enabled when entering Standby mode (by
clearing the nSTDBY_RST bit in the user system data area); this type of reset is also enabled
when entering Deepsleep mode (by clearing the nDEPSLP_RST in the user system data area).
POR reset: power-on reset
LVR reset: low voltage reset
When exiting Standby mode
NRST reset, WDT reset, WWDT reset, software reset and low-power management reset sets all
registers to their reset values except the clock control/status register (CRM_CTRLSTS) and the battery
powered domain; the power-on reset, low-voltage reset or reset generated when exiting Standby mode
sets all registers to their reset values except the battery powered domain registers.
