AT32F425
Series Reference Manual
2022.03.30
Page 369
Ver 2.01
of the NAK status bit and EPENA bit in the OTGFS_DOEPCTLx register. The SUPCNT bit is
decremented each time the control endpoint receives a SETUP packet. If the SUPCNT bit is not
programmed to a proper value before receiving a SETUP packet, the controller still receives the
SETUP packet and decrementes the SUPCNT bit, but the application may not be able to determine
the exact number of SETUP packets received in the SETUP stage of a control transfer.
OTGFS_DOEPTSIZx.SUPCNT = 0x3
2. The application must allocate some extra space for the receive data FIFO to ensure that up to three
SETUP packets can be received on a control endpoint
The space to be reserved is 13 DWORDs. Four DWORDs are required for one SETUP packet,
one DWORD is required for the Setup stage and 8 DWORDs are required to store two extra SETUP
packets among all control endpoints
Four DWORDs per SETUP packet are required to store 8-byte SETUP data and 4-byte Transfer
completed status and 4-byte SETUP status (SETUP packet mode). The controller must reserve this
space to receive data
FIFO is used to write SETUP data only, and never for data packets
3. The application must read 2-DWORDs SETUP packet from the receive data
4. The application must read and discard the Transfer Completed status DWORD from the receive FIFO,
and ignore the Transfer Completed interrupt due to this read operation.
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Internal data flow
】
1. When a SETUP packet is received, the controller writes the received data to the receive FIFO, without
checking whether there is available space in the receive FIFO, irrespective of the NAK and Stall bits on
the control endpoints.
The controller sets the IN NAK and OUT NAK bits for the control IN/OUT endpoints on which the
SETUP packet was received.
2. For every SETUP packet received on the USB line, 3 DWORDs of data are written to the receive
FIFO, and the SUPCNT bit is decremented by 1 automatically.
The first DWORD contains control information used internally by the controller
The second DWORD contains the first 4 bytes of the SETUP command
The third DWORD contains the last 4 bytes of the SETUP command
3. When the SETUP stage switches to data IN/OUT stage, the controller writes a SETUP status done
DWORD to the receive FIFO, indicating the end of the SETUP stage.
4. The application reads the SETUP packegs through the AHB bus.
5. When the application pops the Setup stage done DWORD from the receive FIFO, the controller
interrupts the application through the SETUP interrupt bit in the OTGFS_DOEPINTx register, indicating
that the application can start processing the SETUP packet received.
6. The controller clears the endpoint enable bit for control OUT endpoints.
【
Application programming process
】
1. Program the OTGFS_DOEPTSIZx register
OTGFS_DOEPTSIZx.SUPCNT = 0x3
2. Wait for the RXFLVL interrupt bit in the OTGFS_GINTSTS register and read and empty the data
packets from the receive FIFO (Refer to Read FIFO packets for details). This operation can be repeated
several times.
3. When the SETUP interrupt bit is set in the OTGFS_DOEPINTx register, it indicates that the SETUP
data transfer has been completed successfully. Upon this interrupt, the application must read the
OTGFS_DOEPTSIZx register to determine the number of SETUP packets received, and process the
last received SETUP packet.