AT32F425
Series Reference Manual
2022.03.30
Page 354
Ver 2.01
receive FIFO
7.
The application must read the receive packet status, and ignore it when the receive packet status is
not an IN data packet
8.
The controller generats the XFERC interrupt as soon as the receive packet is read
9.
To handle the XFERC interrupt, disable the channel (see Halting a channel) and stop writing the
OTGFS_HCCHAR2 register. The controller writes a channel halted request to the non-periodic
request queue once the OTGFS_HCCHAR2 register is written
10.
The controller generates the RXFLVL interrupt as soon as the halt status is written to the receive
FIFO
11.
Read and ignore the receive packet status
12.
The controller generates a CHHLTD interrupt as soon as the halt status is read from the receive
FIFO
13.
In response to the CHHLTD interrupt, the processor does not allocate the channel for other transfers.
（
2
）
Handling interrupts
The following code describes the interrupt service routine related to the channel during bulk and control
IN transfers
Unmask (XACTERR/XFERC/BBLERR/STALL/DATATGLERR)
if (XFERC)
{
Reset Error Count
Unmask CHHLTD
Disable Channel
Reset Error Count
Mask ACK
}
else if (XACTERR or BBLERR or STALL)
{
Unmask CHHLTD
Disable Channel
if (XACTERR)
{
Increment Error Count
Unmask ACK
}
}
else if (ChHltd)
{
Mask CHHLTD
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel
}
}
else if (ACK)
{
Reset Error Count
