AT32F425
Series Reference Manual
2022.03.30
Page 387
Ver 2.01
USB Turnaround Time
This field sets the turnaround time in PHY clocks. It defines
the response time when the MAC sends a request to the
packet FIFO controller (PFC) to fetch data from the DFIFO
(SPRAM). These bits must be configured as follows:
0101: When the MAC interface is 16-bit UTMI+
1001: When the MAC interface is 8-bit UTMI+
Note: The aforementioned values are calculated based on
a minimum of 30MHz AHB frequency. The USB turnaround
time is critical for certifications with long cables and 5-Hub.
If you want the AHB to run below 30 MHz, and don’t care
about the USB turnaround time, you can set larger values
for these bits.
Bit 9: 3
Reserved
0x00
resd
Kept at its default value.
Bit 2: 0
TOUTCAL
0x0
rw
Accesible in both host mode and device modes
FS Timeout calibration
The number of PHY clocks that the application programs
in these bits is added to the full-speed interpacket timeout
duration in order to compensate for any additional latency
introduced by the PHY. This action can be required,
because the delay triggered by the PHY while generating
the line state condition can vary from one PHY to another.
In full-speed mode, the USB standard timeout value is
16~18 (inclusive) bit times. The application must program
these bits based on the enumeration speed. The number
of bit times added per PHY clock is 0.25 bit times.
20.6.3.5 OTGFS reset register (OTGFS_GRSTCTL)
The application resets various hardware modules in the controller through this register.
Bit
Register
Reset value
Type
Description
Bit 31
AHBIDLE
0x1
ro
Accesible in both host mode and device modes
AHB master Idle
This bit indicates that the AHB master state machine is in
idle condition.
Bit 30: 11 Reserved
0x000
resd
Kept at its default value.
Bit 10: 6
TXFNUM
0x00
rw
Accesible in both host mode and device modes
TxFIFO number
This field indicates the FIFO number that must be
refreshed through the TxFIFO Flush bit. Do not make
changes to this field until the controller clears the TxFIFO
Flush bit.
00000:
- Non-periodic TxFIFO in host mode
- Tx FIFO 0 in device mode
00001:
- Periodic TxFIFO in host mode
- TXFIFO 1 in device mode
00010:
- TXFIFO 2 in device mode
...
01111:
- TXFIFO 15 in device mode
10000:
- Refresh all the transmit FIFOs in device or host mode
Bit 5
TXFFLSH
0x0
rw1s
Accesible in both host mode and device modes
TxFIFO Flush
This bit selectively refreshes a single or all transmit FIFOs,
but can do so when the controller is not in the process of a
transaction.
The application must write this bit only after checking that
the controller is neither writing to nor reading from the
TxFIFO.
Verify using these registers:
Read: NAK effective interrupt (NAK Effective Interrupt)
