AT32F425
Series Reference Manual
2022.03.30
Page 307
Ver 2.01
Figure 18-10 Oversampling of preempted group of channels
ADC_IN0
ADC_IN0
PCCE flag set
OOSEN = 1, POSEN = 1, OOSRSEL = 0, OOSTREN = 0,
PCAUTOEN = 1, SQEN = 1
Ordinary
trigger
1
st
2
nd
3
rd
ADC_IN0
Ordinary
Preempted
OCLEN=0, OSN1=ADC_IN0
PCLEN=1, PSN3=ADC_IN4, PSN4=ADC_IN5
ADC_IN0
4
th
ADC_IN4
ADC_IN4
1
st
2
nd
3
rd
ADC_IN4
ADC_IN4
4
th
ADC_IN5
ADC_IN5
1
st
2
nd
3
rd
ADC_IN5
ADC_IN5
4
th
OCCE flag set
Sampling
Conversion
18.4.5 Data management
At the end of the conversion of the ordinary group, the converted value is stored in the ADC_ODT register.
Once the preempted group conversion ends, the converted data of the preempted group is stored in the
ADC_PDTx register.
18.4.5.1 Data alignment
DTALIGN bit in the ADC_CTRL2 register selects the alignment of data (right-aligned or left-aligned).
Apart from this, the converted data of the preempted group is decreased by the offset written in the
ADC_PCDTOx register. Thus the result may be a negative value, marked by SIGN.
The data are aligned on a half-word basis expect when the resolution is set to 6-bit. In this case, the
data are aligned on a byte basis, as shown in
Figure 18-11 Data alignment
SIGN
SIGN
SIGN
SIGN
DT[11] DT[10]
DT[9]
DT[8]
DT[7]
DT[6]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
SIGN DT[11] DT[10]
DT[9]
DT[8]
DT[7]
DT[6]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
0
0
0
0
0
0
0
DT[11] DT[10]
DT[9]
DT[8]
DT[7]
DT[6]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
DT[11] DT[10]
DT[9]
DT[8]
DT[7]
DT[6]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
0
0
0
0
Preempted channel data 12 bits
Right-alignment
Ordinary channel data 12 bits
Right-alignment
Left-alignment
Left-alignment
18.4.5.2 Data read
Read access to the ADC_ODT register using CPU or DMA gets the converted data of the ordinary group.
Read access to the ADC_PDTx register using CPU gets the converted data of the preempted group.
When the OCDMAEN bit is set in the ADC_CTRL2 register, the ADC will issue DMA requests each time
the ADC_OTD register is updated.
18.4.6 Voltage monitoring
The OCVMEN bit or PCVMEN bit in the ADC_CTRL1 register is used to enable voltage monitoring based
on the converted data.
The VMOR bit will be set if the converted result is outside the high threshold (ADC_VMHB register) or
less than the low threshold (ADC_VMLB register).
The VMSGEN bit in the ADC_CTRL1 register is used to enable voltage monitor on either a single
channel or all the channels. The VMCSEL bit is used to select a specific channel that requires voltage
monitoring.
Voltage monitoring is based on the comparison result between the original converted data and the 12-
bit voltage monitor boundary register, irrespective of the CRSEL, PCDTOx and DTALIGN bits.
When using an oversampler, voltage monitoring is based on the comparison result between the 16-bit
registes (ADC_VMHB[15:0] and ADC_VMLB[15:0]) and the oversampled data.
