AT32F425
Series Reference Manual
2022.03.30
Page 152
Ver 2.01
12.7
Transmitter
12.7.1 Transmitter introduction
USART transmitter has its individual TEN control bit. The transmitter and receiver share the same baud
rate that is programmable. There is a transmit data buffer (TDR) and a transmit shift register in the
USART. The TDBE bit is set whenever the TDR is empty, and an interrupt is generated if the TDBEIEN
is set.
The data written by software is stored in the TDR register. When the shift register is empty, the data will
be moved from the TDR register to the shift register so that the data in the transmit shift register is output
on the TX pin in LSB mode. The output format depends on the programmed frame format.
If synchronous transfer or clock output is selected, the clock pulse is output on the CK pin. If the hardware
flow control is selected, the control signal is input on the CTS pin.
Note: 1. The TEN bit cannot be reset during data transfer, or the data on the TX pin will be
corrupted.
2. After the TEN bit is enabled, the USART will automatically send an idle frame.
12.7.2 Transmitter configuration
1. USART enable: Set the UEN bit.
2. Full-duplex/half-duplex configuration: Refer to full-duplex/half-duplex selector for more information.
3. Mode configuration: Refer to mode selector for more information.
4. Frame format configuration: Refer to frame format for more information.
5. Interrupt configuration: Refer to interrupt generation for more information.
6. DMA transmission configuration: If the DMA mode is selected, the DMATEN bit (bit 7 in the
USART_CTRL3register) is set, and configure DMA register accordingly.
7. Baud rate configuration: Refer to baud rate generation for details.
8. Transmitter enable: When the TEN bit is set, the USART transmitter will send an idle frame.
9. Write operation: Wait unitl the TDBE bit is set, the data to be transferred will be loaded into the
USART_DT register (This operatin will clear the TDBE bit). Repeat this step in non-DMA mode.
10. After the last data expected to be transferred is written, wait until the TDC is set, indicating the end
of transfer. The USART cannot be disabled before the flag is set, or transfer error will occur.
11. When TDC=1, read access to the USART_STS register and write access to the USART_DT
register will clear the TDC bit; This bit can also be cleared by writing “0”, but this is valid only in
DMA mode.
12.8
Receiver
12.8.1 Receiver introduction
USART receiver has its individual REN control bit (bit 2 in the USART_CTRL1 register). The
transmitter and receiver share the same baud rate that is programmable. There is a receive data buffer
(RDR) and a receive shift register in the USART.
The data is input on the RX pin of the USART. When a valid start bit is detected, the receiver ports the
data received into the receive shift register in LSB mode. After a full data frame is received, based on
the programmed frame format, it will be moved from the receive shift register to the receive data buffer,
and the RDBF is set accordingly. An interrupt is generated if the RDBFIEN is set.
If hardware flow control is selected, the control signal is output on the RTS pin.
During data reception, the USART receiver will detect whether there are errors to occur, including
framing error, overrun error, parity check error or noise error, depending on software configuration, and
whether there are interrupts to generate using the interrupt enable bits.
