AT32F425
Series Reference Manual
2022.03.30
Page 362
Ver 2.01
an IN packet (GRXSTSR.PKTSTS!= 0x0010)
8. The controller generates an XFERC interrupt as soon as the receive packet is read
9. To handle the XFERC interrupt, read the PKTCN bit in the OTGFS_HCTSIZ2 register. If the PKTCNT
bit in the OTGFS_HCTSIZ2 is not equal to 0, disable the channel before re-initializing the channel for
the next transfer. If PKTCNT == 0 in the OTGFS_HCTSIZ2 register, re-initialize the channel for the next
transfer. In this case, the application must reset the ODDFRM bit in the OTGFS_HCCHAR2 register.
（
2
）
Handling interrupts
The following code describes the interrupt service routine related to the channel during synchronous IN
transfers
Unmask (XACTERR/XFERC/FRMOVRUN/BBLERR)
if (XFERC or FRMOVRUN)
{
if (XFERC and (HCTSIZx.PKTCNT == 0))
{
Reset Error Count
De-allocate Channel
}
else
{
Unmask CHHLTD
Disable Channel
}
}
else if (XACTERR or BBLERR)
{
Increment Error Count
Unmask CHHLTD
Disable Channel
}
else if (CHHLTD)
{
Mask CHHLTD
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel
}
}
20.5.3.12
Initialize synchronous OUT transfers
shows a typical synchronous OUT transfer operation. Refer to channel 1 (ch_1). The
assumptions are as follows:
The application is attempting to send one largest-packet-size packet (transfer size is 1023 bytes)
to every frame from the next odd frame
The periodic transmit FIFO can store one packet (1KB bytes for full-speed transfer)
The periodic request queue depth is 4
（
1
）
Common interrupt IN operation process
The sequence of operations shown in Figure 21-9 (channel 2) is as follows:
