AT32F425
Series Reference Manual
2022.03.30
Page 412
Ver 2.01
frame
1: Set DATA1 PID enabled or forced odd frame
Bit 28
SETD0PID/
SETEVENFR
0x0
rw
Set DATA0 PID
Applies to interrupt/bulk OUT endpoints only. Writing to this
bit sets the endpoint data PID bit in this register to DATA0.
Set Even frame
Applies to synchronous OUT endpoints only. Writing to this
bit sets the Even/Odd frame to even frame.
0:Disabled Set DATA0 PID disabled or Do not force
evem frame
1: Set DATA0PID or set the EOFRNUM to even frame
Bit 27
SNAK
0x0
wo
Set NAK
A write to this bit sets the NAK bit for the endpoint. The
application uses this bit to control the transmission of NAK
handshakes on an endpoint. The controller sets this bit on
a Transfer completed interrupt or after receiving a SETUP
packet.
Values:
0: Do not set NAK
1: Set NAK
Bit 26
CNAK
0x0
wo
Clear NAK
A write to this bit clears the NAK bit for the endpoint.
0: Not clear NAK
1: Clear NAK
Bit 25: 22 Reserved
0x0
resd
Kept at its default value.
Bit 21
STALL
0x0
rw
Applies to non-control, non-synchronous IN and OUT
endpoints.
The application sets this bit to stall all tokens from the USB
host to this endpoint. If a NAK bit , glocal non-periodic IN
NAK bit or global OUT NAK bit is set along with this bit, the
STALL bit has priority. Only the application can clear this
bit, but the controller never.
Bit 20
SNP
0x0
rw
Snoop mode
This bit configures the endpint to Snoop mode. In this
mode, the controller does not check the correctness of
OUT packets before transmitting OUT packets to the
application memory.
Bit 19: 18 EPTYPE
0x0
rw
Endpoint type
This is the transfer type supported by this logical endpoint.
00: Control
01: Synchronous
10: Bulk
11: Interrupt
Bit 17
NAKSTS
0x0
ro
NAK status
Indicates the followins:
0: The controller is sending non-NAK handshakes based
on the FIFO status
1: The controller is sending NAK handshakes
–
When this bit is set (either by the application or the
controller), the controller stops receiving any data on an
OUT endpoint, even if there is space in the receive FIFO
to accommodate the incoming data packets.
–
For non-synchronous IN endpoints: the controller stops
transmitting data on the endpoint, even if there is data
pending in the transmit FIFO.
–
For synchronous IN endpints: the controller sends a zero-
length data packet, even if there is space in the transmit
FIFO.
–
The controller always responds to SETUP data packets
with an ACK handshake, regardless of whether this bit is
set or not.
Bit 16
DPID/
EOFRNUM
0x0
ro
Endpoint data PID
Applies to interrupt/bulk OUT endpoints only.
This bit contains the PID of the packet to be transmitted on