AT32F425
Series Reference Manual
2022.03.30
Page 390
Ver 2.01
Control and Status register to clear this bit.
Bit 23: 22 Reserved
0x0
resd
Kept at its default value.
Bit 21
INCOMPIP
INCOMPISOOUT
0x0
rw1c
Incomplete periodic transfer
Accesible in host mode only
In host mode, the controller sets this interrupt bit when
there are incomplete periodic transfers still pending in the
current frame.
Incomplete Isochronous OUT Transfer
Accesible in device mode only
In device mode, the controller sets this interrupt bit to
indicate that there is at least one synchronous OUT
endpoint with incomplete transfers in the current frame.
This interrupt is generated along with the End of Periodic
Frame Interrupt interrupt bit in this register.
Bit 20
INCOMPISOIN
0x0
rw1c
Accesible in device mode only
Incomplete Isochronous IN Transfer
The controller sets this interrupt to indicate that there is at
least one synchronous IN endpoint with incomplete
transfers in the current frame. This interrupt is generated
along with the End of Periodic Frame Interrupt interrupt bit
in this register.
Bit 19
OEPTINT
0x0
ro
Accesible in device mode only
OUT endpoints interrupt
The controller sets this bit to indicate that an interrupt is
pending on one of the OUT endpoints in the controller. The
application must read the Device All Endpoints Interrupt
register to determine the exact number of the OUT
endpoint on which the interrupt occurred, and then read
the corresponding Device OUT Endpoint-n Interrupt
register to determine the exact source of the interrupt. The
application must clear the corresponding status bit in the
corresponding Device OUT Endpoint-n Interrupt register to
clear this bit.
Bit 18
IEPTINT
0x0
ro
Accesible in device mode only
IN Endpoints interrupt
The controller sets this bit to indicate that an interrupt is
pending one of the IN endpoints in the controller (in device
mode). The application must read the Device All Endpoints
Interrupt register to determine the exact number of the IN
endpoint on which the interrupt occurred, and then read
the corresponding Device IN Endpoint-n Interrupt register
to determine the exact source of the interrupt. The
application must clear the corresponding status bit in the
corresponding Device IN Endpoint-n Interrupt register to
clear this bit.
Bit 17: 16 Reserved
0x0
resd
Kept at its default value.
Bit 15
EOPF
0x0
rw1c
Accesible in device mode only
End of periodic frame interrupt
This bit indicates that the period programmed in the
periodic frame interval bit of the Device Configuration
register has been reached in the current frame.
Bit 14
ISOOUTDROP
0x0
rw1c
Accesible in device mode only
Isochronous OUT packet dropped interrupt)
The controller sets this bit on the following condition:the
controller fails to write a synchronous OUT packet into the
receive FIFO because the receive FIFO does not have
enough space to accommodate a maximum size packet
for the synchronous OUT endpoint.
Bit 13
ENUMDONE
0x0
rw1c
Accesible in device mode only
Enumeration done
The controller sets this bit to indicate that speed
enumeration is done.
The application must read the Device Status register to
obtain the enumeration speed.