ARTERY AT32F425 Series, Reference Manual

Page: 144 / 429

AT32F425 Series Reference Manual
2022.03.30 Page 144 Ver 2.01
1: 10-bit address mode
Bit 9: 0 ADDR1[9: 0] 0x000 rw
Own address1
In 7-bit address mode, bit 0 and bit [9
： 8] don’t care.
11.7.4 Own address register2 (I2C_OADDR2)
Bit Register Reset value Type Description
Bit 31: 16 Reserved 0x000 res Kept at its default value.
Bit 15 ADDR2EN 0x0 rw
Own address 2 enable
0: Own address 2 disabled
1: Own address 2 enabled
Bit 14: 11 Reserved 0x0 res Kept at its default value
Bit 10: 8 ADDR2MASK[2: 0] 0x0 rw
Own address 2-bit mask
000: Match Address bit [7: 1]
001: Match Address bit [7: 2]
010: Match address bit [7: 3]
011: Match address bit [7: 4]
100: Match address bit [7: 5]
101: Match address bit [7: 6]
110: Match address bit [7]
111: Response all addresses other than those reserved for
I2C
Bit 7: 1 ADDR2[7: 1] 0x00 rw
Own address 2
7-bit address mode
Bit 0 Reserved 0x0 res Kept at its default value.
11.7.5 Timing register (I2C_CLKCTRL)
Bit Register Reset value Type Description
Bit 31: 28 DIVL[3: 0] 0x0 rw Low 4 bits of clock divider value
Bit 27: 24 DIVH[7: 4] 0x0 rw
High 4 bits of clock divider value
DIV = (DIVH << 4) + DIVL
Bit 23: 20 SCLD[3: 0] 0x0 rw
SCL output delay
T
SCLD
= (SCLD + 1) x (DIV + 1) x T
I2C_CLK
Bit 19: 16 SDAD[3: 0] 0x0 rw
SDA output delay
T
SDAD
= (SDAD + 1) x (DIV + 1) x T
I2C_CLK
Bit 15: 8 SCLH[7: 0] 0x00 rw
SCL high level
T
SCLH
= (SCLH + 1) x (DIV + 1) x T
I2C_CLK
Bit 7: 0 SCLL[7: 0] 0x00 rw
SCL low level
T
SCLL
= (SCLL + 1) x (DIV + 1) x T
I2C_CLK
11.7.6 Timeout register (I2C_TIMEOUT)
Bit Register Reset value Type Description
Bit 31 EXTEN 0x0 rw
Cumulative clock low extend timeout enable
0: Cumulative clock low extend timeout disabled
1: Cumulative clock low extend timeout enabled
Corresponds to T
LOW:SEXT
/ T
LOW:MEXT
in SMBus
Bit 30: 28 Reserved 0x0 res Kept at its default value.
Bit 27: 16 EXTTIME[11:0] 0x000 rw
Cumulative clock low extend timeout value
Timeout duration = (E 1) x 2048 x T
I2C_CLK
。
Bit 15 TOEN 0x0 rw
Detect clock low/high timeout enable
0: Clock low/high timeout detection disabled
1: clock low/high timeout detection enabled
Corresponds to T
TIMEOUT
in SMBus.
Bit 14: 13 Reserved 0x0 res Kept at its default value.
Bit 12 TOMODE 0x0 rw
Clock timeout detection mode
0: Clock low level detection
1: Clock high level detection
Bit 11: 0 TOTIME[11:0] 0x000 rw
Clock timeout detection time
For clock low level detection (TOMODE = 0):
Timeout duration = ( 1) x 2048 x T
I2C_CLK
For clock high level detection (TOMODE = 1):
Timeout duration = ( 1) x 4 x T
I2C_CLK