AT32F425
Series Reference Manual
2022.03.30
Page 374
Ver 2.01
Figure 20-12 BULK OUT transfer block diagram
3
4
xact_1
5
Application
Host
USB
Device
idle until intr
512 bytes
2
7
int_out_ep
wr_reg(DOEPTSIZn)
wr_reg(DOEPCTLn)
1
rcv_out_pkt()
idle until intr
6
8
On new xfer or
RXFIFO not
empty
XFERSIZE = 512bytes
PKTCNT = 1
EPENA = 1
CNAK = 1
After a SetConfiguration/SetInterface command is received, the application initializes all OUT endpoints
by setting CNAK = 0x1 and EPENA = 0x1 in the OYG_DOEPCTLx register, and setting the XFERSIZE
and PKTCNT bits in the OTGFS_DOEPTSIZx register.
1. The host attempts to send data (OUT token) to the endpoint
2. When the controller receives the OUT token on the USB, it stores data in the receive FIFO because
the FIFO has free space.
3. Upon writing the complete data in the receive FIFO, the controller then triggers the RXFLVL interrupt
bit in the OTGFS_GINTSTS register.
4. Upon receiving the packet count of USB packets, the controller internally sets the NAK bit for the
endpoint to prevent it from receiving any more packets.
5. The application processes the interrupt and reads the data from the receive FIFO.
6. When the application reads all the data (equivalent to XFERSIZE), the controller generates an XFERC
interrupt in the OTGFS_DOEPINTx register.
7. The application processes the interrupt and uses the XFERC bit in the OTGFS_DOEPINTx register
to judge that the expected transfer is already complete.
20.5.4.16
Synchronous OUT data transfers
To initialize the controller after power-on reset, the application must perform the steps list in “OTGFS
Initialization”. Before communicating with a host, the application must initialize endpoints based on the
process described in “Endpoint Initialization” and by referring to “Read FIFO packets”. This section
describes a regular synchronous OUT transfers.
【
Application requirements
】
1. All the application requirements are the same as that of non-synchronous OUT data transfers.
