AT32F425
Series Reference Manual
2022.03.30
Page 118
Ver 2.01
Address reception: The SCL clock is not stretched when the address received by
slave
matches the local address enabled (ADDRF=1 in the I2C_STS)
Data reception: If there is data to be read in the I2C_RXDT register before the next ACK signal,
an overflow will occur, and the OUF bit will also be set in the I2C_STS register
Data transmission: If no data is written to the I2C_TXDT regisuter after the completion of the
previous data transfer, an underflow will occur, and the OUF will also be set in the I2C_STS register
11.4.1 I
2
C timing control
I
2
C core is clocked by I2C_CLK whereas the I2C_CLK is clocked by PCLK1. The PCLK1 should be set
to be less than 4/3 SCL cycles.
The corresponding bits in the I2C_CLKCTR register are used for timing configuration.
— DIV[7: 0]: I2C clock divider
— SDAD[3: 0]: Data hold time (t
HD
;DAT)
— SCLD[3: 0]: Data setup time (t
SU
;DAT)
— SCLH[7: 0]: SCL high
— SCLL[7: 0]: SCL low
Note: Timing configuration cannot be modified once the I
2
C is enabled.
Figure 11-3 Setup and hold time
It is possible to configure data hold time (t
HD;DAT
) and data setup time (t
SU;DAT
) freely by setting the DIV[7:
0], SDAD[3: 0] and SCLD[3: 0] in the I2C_CLKCTRL register.
Data hold time (t
H D ; D A T
):
refers to the duration from SCL falling edge to SDA output
t
HD;DAT
= t
SDAD
+ t
SYNC
t
SDAD
= SDAD x (DIV + 1) x t
I2C_CLK
t
SYNC
= (DLFT + 3) x t
I2C_CLK
- t
f
t
SYNC
consists of three parts:
―
SCL falling edge time t
f
―
Digital filter input latency (DLFT x t
I2 C _ C L K
)
―
Synchronization delay between SCL and I2C_CLK (2~3 I2C_CLK cycles)
Data setup time (t
S U ; D AT
):
refers to the duration from SDA output to SCL rising edge
t
SU;DAT
= SCLD x (DIV+1) x t
I2C_CLK
– t
r
SCLD
T
SU;DAT
Data setup
time
T
HD;DAT
Data hold
time
SCL falling edge
internal detection
tSYNC1
SDAD
SCL
SDA
tSYNC2
SCLH
tSYNC1
SCLL
SCL high level detected
SCLH counter starts
SCL drive low
SCL low level detected
SCLL counter starts
SCL release
