AT32F425
Series Reference Manual
2022.03.30
Page 346
Ver 2.01
2. Program the following fields in the global AHB configuration register:
OTGFS_GINTMSK.RXFLVLMSK = 0x0
3. Program the following fields in the OTGFS_GUSBCFG register:
Full-speed timeout standard bit
USB turnaround time bit
4. The software must unmask the following bits in the OTGFS_GINTMSK register:
OTG interrupt mask
Mode mismatch interrupt mask
5. The software can read the CURMOD bit in the OTGFS_GINTSTS register to determine
whether the OTGFS controller is operating in host or device mode.
20.5.2 OTGFS FIFO configuration
20.5.2.1 Device mode
A dynamic FIFO alloction is required during power-on or USB reset. In device mode, the application
must meet the following conditions before modifying FIFO SRAM allocation.
OTGFS_DIEPCTLx/ OTGFS_DOEPCTLx.EPENA = 0x0
OTGFS_DIEPCTLx/ OTGFS_DOEPCTLx.NAKSTS = 0x1
The TXFNUM bit in the OTGFS_GRSTCTL register is used to refresh the controller transmit FIFO. Refer
to Section Refresh controller transmit FIFO for more information.
Attention should be paid to the following information during FIFO SRAM allocation:
（
1
）
Receive FIFO SRAM allocation
SRAM for SETUP Packets: 13 DWORDs must be reserved in the receive FIFO to receive one
SETUP Packet on control endpoint. The controller does not use these locations, which are reserved
for SETUP packets.
One DWORD is to be reserved for global OUT NAK
Status information is written to the FIFO along with each received packet. Therefore, a minimum
space of (largest packet size/4) + 1 must be allocated to receirve data packets. In most cases, two
(largest packet size/4) + 1 spaces are recommended so that the USB can receive the subseqnet
packet while the previous packet is being transferred to the AHB. If there is a longer latecy on AHB,
sufficient spaces must be reserved to receive multiple packets in order to prevent synchronous data
packet loss.
Transfer complete status information, along with the last packet for each endpoint, is also pushed
to the FIFO
One location must be reserved for the disable status bit of each endpoint
Typically, two DWORDs for each OUT endpoint are recommended.
（
2
）
Transmit FIFO SRAM allocation
The minimum SRAM space required for each IN endpoint transmit FIFO is the maximum data packet
size for that particular IN endpoint. The more the space allocated to the transmit IN endpoint FIFO, the
better the USB performance, and this helps to avoid latency on the AHB line.
Table 20-2 OTGFS transmit FIFO SRAM allocation
FIFO name
SRAM size
Receive FIFO
rx_fifo_size, including setup packets, OUT endpoint control
information and OUT data packets.
Transmit FIFO 0
tx_fifo_size[0]
Transmit FIFO 1
tx_fifo_size[1]
Transmit FIFO 2
tx_fifo_size[2]
……
……
Transmit FIFO i
tx_fifo_size[i]
Configure the following registers according to the above mentioned:
1. OTGFS receive FIFO size register (OTGFS_GRXFSIZ)
OTGFS_GRXFSIZ.RXFDEP = rx_fifo_size
2. Endpoint 0 TX FIFO size register (OTGFS_DIEPTXF0)
OTGFS_DIEPTXF0.INEPT0TXDEP = tx_fifo_size[0]
；
OTGFS_DIEPTXF0.INEPT0TXSTADDR = rx_fifo_size
；
