AT32F425
Series Reference Manual
2022.03.30
Page 257
Ver 2.01
restarts from 0, and generates a counter overflow event, with the OVFIF bit being set. If the overflow
event is disabled, the register is no longer reloaded with the preload and re-loaded value after counter
overflow occurs, otherwise, the prescaler and re-loaded value will be updated at an overflow event.
Figure 14-82
Overflow event when PRBEN=0
0
1
2
3
...
31
32
0
1
2
3
...
31
32
0
1
2
3
COUNTER
31
32
0
1
32
...
PR[15:0]
OVFIF
TMR_CLK
0
DIV[15:0]
22
Clear
Clear
Clear
Figure 14-83
Overflow event when PRBEN=1
0
1
2
3
...
21
22
0
1
2
3
...
31
32
0
1
2
3
COUNTER
31
32
0
1
32
...
PR[15:0]
OVFIF
TMR_CLK
0
DIV[15:0]
22
Clear
Clear
Clear
Downcounting mode
In downcounting mode, the counter counts from the value programmed in the TMRx_PR register down
to 0, and restarts from the value programmed in the TMRx_PR register, and generates a counter
underflow event.
Figure 14-84
Counter timing diagram with internal clock divided by 4
TMR_CLK
CNT_CLK
COUNTER
OVFIF
0
1
2
3
4
DIV[15
：
0]
32
31
30
32
PR[15
：
0]
Clear
Up/down counting mode
In up/down counting mode, the counter counts up/down alternatively. When the counter counts from the
value programmed in the TMRx_PR register down to 1, an underflow event is generated, and then
restarts counting from 0; when the counter counts from 0 to the value of the TMRx_PR register -1, an
overflow event is generated, and then restarts counting from the value of the TMRx_PR register. The
OWCDIR bit indicates the current counting direction.
Note: The OWCDIR is ready-only in up/down counting mode.
