AT32F425
Series Reference Manual
2022.03.30
Page 375
Ver 2.01
2. For synchronous OUT data transfers, the transfer size and packet count must be set to the number
of the largest-packet-size packets that can be received in a single frame and not exceed this size.
Synchronous OUT data transfer cannot span more than one frame.
1 ≤ packet count [epnum] ≤ 3
3. If the device supports the synchronous OUT endpoints, the application must read all synchronous
OUT data packets from the receive FIFO before the end of the periodic frame (EOPF interrupt in the
OTGFS_GINTSTS register)
4. To receive data in the subsequent frame, an synchronous OUT endpoint must be enabled before the
generation of the EOPF and SOF interrupt in the OTGFS_GINTSTS register.
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Internal data flow
】
1. The internal data flow for the synchronous OUT endpoints is the same as that for the non-synchronous
OUT endpoints, just for a few differences.
2. When the synchronous OUT endpoint is enabled by setting the endpoint enable bit and by clearing
the NAK bit, the even/odd frame bits are also set properly. The controller can receive data on an
synchronous OUT endpoint in a particular frame only when the following condition is met:
Even/Odd microframe (OTGFS_DOEPCTLx) =SOFFN[0] (OTGFS_DSTS)
3. When the application completely reads the synchronous OUT data packet (data and status) from the
receive FIFO, the controller updates the RXDPID bit in the OTGFS_DOEPTSIZx register based on the
data PID of the last synchronous OUT data packet read from the receive FIFO.
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Application programming sequence
】
1. Program the transfer size and the corresponding packet count of the OTGFS_DOEPTSIZx register
2. Program the OTGFS_DOEPCTLx register with the endpoint enable, ClearNAK and Even/Odd frame
bits
Endpoint enable = 0x1
CNAK = 0x1
Even/Odd frame = (0x0: Even; 0x1: Odd)
3. Wait for the RXFLVL interrupt in the OTGFS_GINTSTS register, and read all the data packets from
the receive FIFO. See “Read FIFO” for more information
This step can be repeated several times, depending on the transfer size
4. When the XFERC interrupt is set in the OTGFS_DOEPINTx register, it indicates the completion of the
synchronous OUT data transfers. But this interrupt does not necessarily mean that the data in memory
are good.
5. This interrupt signal cannot always be detected by the synchronous OUT data transfers. However, the
application can detect the INCOMPISOOUT interrupt in the OTGFS_GINTSTS register. See “Incomplete
synchronous OUT data transfers” for more information.
6. Read the OTGFS_DOEPTSIZx register to determine the received transfer size and to determine
whether the data received in the frame are valid or not. The application must treat the data received in
memory as valid only when one of the following conditions is met:
OTGFS_DOEPTSIZx.RxDPID = 0xD0 and the USB packet count in which the payload was
received =0x1
OTGFS_DOEPTSIZx.RxDPID = 0xD1 and the USB packet count in which the payload was
received =0x2
OTGFS_DOEPTSIZx.RxDPID = 0xD2 and the USB packet count in which the payload was
received =0x3
The number of USB packets in which the payload was received= Application-programed initial packet
count – Controller-updated final packet count
The application discards invalid data packets.
20.5.4.17
Enable synchronous endpoints
After sending a Set interface control command to the device, a host enables the synchronous endpoints.
Then the host can send the initial synchronous IN token in any frame before transmission in the
sequence of BInterval.
Instead, synchronous support in the OTGFS controller is based on a single-transfer level. The application
must re-configure the controller on every frame. The OTGFS controller enables the synchronous
