AT32F425
Series Reference Manual
2022.03.30
Page 400
Ver 2.01
resume/remote wakeup detected interrupt bit or
disconnect detected interrupt bit in the controller interrupt
register.
The controller can still clear this bit, even if the device is
disconnected with the host.
0: Port not in suspend mode
1: Port in suspend mode
Bit 6
PRTRES
0x0
rw
Port resume
The application sets this bit to drive resume signaling on
the port. The controller continues to trigger the resume
signal until the application clears this bit. If the controller
detects a USB remote wakeup sequence (as indicated by
the port resume/remote wakeup detected interrupt bit of
the controller interrupt register), the controller starts driving
resume signaling without the intervention of the
application.
The read value of this bit indicates wehter the controller is
currently driving resume signaling.
0: No resume triggered
1: Resume triggered
Bit 5
PRTOVRCCHNG
0x0
rw1c
Port overcurrent change
The controller sets this bit when the status of the port
overcurrent active bit (bit 4) in this register changes. This
bit can only be set by the controller. The application must
write 1 to clear this bit.
Bit 4
PRTOVRCACT
0x0
ro
Port overcurrent active
Indicates the overcurrent status of the port.
0: No overcurrent
1: Overcurrent condition
Bit 3
PRTENCHNG
0x0
rw1c
Port enable/disable change
The controller sets this bit when the status of the port
enable bit 2 in this register changes. This bit can only be
set by the controller. The application must write 1 to clear
this bit.
Bit 2
PRTENA
0x0
rw1c
Port enable
A port is enabled only by the controller after a reset
sequence. This port is enabled by an overcurrent
condition, a disconnected condition ro by the application.
The application cannot set this bit by a register write
operation. It can only clear this bit to disable the port. This
bit does not trigger any interrupt.
0: Port disabled
1: Port enabled
Bit 1
PRTCONDET
0x0
rw1c
Port connect detected
On a device connection detected, the controller sets this
bit using the host port interrupt bit in the controller register.
This bit can only be set by the controller. The application
must write 1 to clear this bit.
Bit 0
PRTCONSTS
0x0
ro
Port connect status
0: No device is connected to the port
1: A device is connected to the port
20.6.4.8 OTGFS host channelx characteristics register
(OTGFS_HCCHARx) (x = 0...15, where x= channel number)
Bit
Register
Reset value
Type
Description
Bit 31
CHENA
0x0
rw1s
Channel enable
This bit is set by the application and cleared by the OTG
host.
0: Channel disabled
1: Channel enabled
Bit 30
CHDIS
0x0
rw1s
Channel disable
The application sets this bit to stop transmitting or
receiving data on a channel, even before the transfer on