General-Purpose Input/Output (GPIO)
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SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
General-Purpose Input/Output (GPIO)
4.1
General-Purpose Input/Output (GPIO)
4.1.1 Introduction
The M3 GPIO module is composed of nine physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, Port H, Port J). The GPIO module
supports up to 72 programmable input/output pins, depending on the peripherals being used.
The module has the following features:
•
Up to 72 GPIOs, depending on configuration
•
Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
•
Fast toggle capable of a change every two clock cycles
•
Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back
access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility with
existing code
•
Programmable control for GPIO interrupts
–
Interrupt generation masking
–
Edge-triggered on rising, falling, or both
–
Level-sensitive on High or Low values
•
Bit masking in both read and write operations through address lines
•
Pins configured as digital inputs are Schmitt-triggered
•
Programmable control for GPIO pad configuration
–
Weak pull-up resistors
–
Open drain enables
–
Digital input enables
In addition to the above nine GPIO blocks, an additional eight GPIO blocks, each corresponding to an
individual GPIO port (Port K, Port L, Port M, Port N, Port P, Port Q, Port R, Port S) are available on this
device. These ports are accessible only by AHB bus and not accessible through the APB bus.
These new ports add an additional 64 GPIOs, bringing the total of available GPIOs on this device to 136,
depending on the configuration. The rest of the features on these 64 GPIOs are the same as above listed
for PortA to PortJ GPIOs.
Note:
On REV0 of this device, PF6_GPIO38 and PF6_GPIO42 are not available for general-purpose
usage but are tied to USB0VBUS and USB0DIM functionality. So on REV0 of this device, the total
available GPIO is 134 instead of 136.
4.1.2 Signal Description
GPIO signals have alternate hardware functions.
lists the GPIO pins and their analog and digital
alternate functions. The USB0VBUS and USB0ID analog signals are configured by clearing the
corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding
AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. The digital alternate hardware
functions are enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL)
and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register
to the numeric encoding.
Important:
All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPUR=0, and GPIOPCTL=0). A Power-On-Reset (POR) or asserting XRS puts the pins
back to their default state.