452
Failure Diagnosis Functions
Section 8-8
When execution condition A goes ON, an error with FAL number 002 is gener-
ated, A402.15 (FAL Error Flag) is turned ON, and A360.02 (FAL Number 002
Flag) is turned ON. Program execution continues.
Errors generated by FAL(006) can be cleared by executing FAL(006) with FAL
number 00 or performing the error read/clear operation from the CX-Programmer.
Operation of FALS(007)
When execution condition B goes ON, an error with FALS number 003 is gen-
erated, and A401.06 (FALS Error Flag) is turned ON. Program execution is
stopped.
Errors generated by FAL(006) can be cleared by eliminating the cause of the
error and performing the error read/clear operation from the CX-Programmer.
8-8-2
Failure Point Detection: FPD(269)
FPD(269) performs time monitoring and logic diagnosis. The time monitoring
function generates a non-fatal error if the diagnostic output isn’t turned ON
within the specified monitoring time. The logic diagnosis function indicates
which input is preventing the diagnostic output from being turned ON.
Time Monitoring
Function
FPD(269) starts timing when it is executed and turns ON the Carry Flag if the
diagnostic output isn’t turned ON within the specified monitoring time. The
Carry Flag can be programmed as the execution condition for an error pro-
cessing block. Also, FPD(269) can be programmed to generate a non-fatal
FAL error with the desired FAL number.
When an FAL error is generated, a preset message will be registered and can
be displayed on the CX-Programmer. FPD(269) can be set to output the
results of logic diagnosis (the address of the bit preventing the diagnostic out-
put from being turned ON) just before the message.
The teaching function can be used to automatically determine the actual time
required for the diagnostic output to go ON and set the monitoring time.
Logic Diagnosis
Function
FPD(269) determines which input bit is causing the diagnostic output to
remain OFF and outputs the result. The output can be set to bit address out-
put (PLC memory address) or message output (ASCII).
If bit address output is selected, the PLC memory address of the bit can be
transferred to an Index Register and the Index Register can be indirectly
addressed in later processing.
B
FALS
003
#0000
Содержание CP1L-EL20DR-D
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Страница 22: ...xxii...
Страница 34: ...xxxiv Software Licenses and Copyrights 7...
Страница 178: ...144 Connecting the CX Programmer Section 5 1 Click the Connect button to connect and then connection online is completed...
Страница 192: ...158 Trial Operation and Debugging Section 5 3...
Страница 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Страница 666: ...632 Trouble Shooting Section 11 7...
Страница 696: ...662 Standard Models Appendix A...
Страница 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Страница 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Страница 836: ...802 PLC Setup Appendix G...
Страница 838: ...804 TCP Status Transitions Appendix H...
Страница 840: ...806 Ethernet Network Parameters Appendix I...
Страница 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Страница 844: ...810 Ethernet Specifications Appendix K...
Страница 851: ...Index 817 work words 118 write protection 447...
Страница 852: ...818 Index...
Страница 854: ...820 Revision History...
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