376
Interrupt Functions
Section 8-1
Interrupt Task Priority
The input interrupts (direct mode and counter mode), high-speed counter
interrupts, scheduled interrupts, and external interrupts all have the same pri-
ority. If interrupt task A (an input interrupt, for example) is being executed
when interrupt task B (a scheduled interrupt, for example) is called, task A
processing will not be interrupted. Task B processing will be started when task
A is completed.
If two different types of interrupt occur simultaneously, they are executed in
the following order:
If two of the same type interrupt occur simultaneously, the task with the lower
interrupt task number is executed first.
Note
If a user program is likely to generate multiple interrupts simultaneously, the
interrupt tasks will be executed in the order shown above, so it may take some
time from the occurrence of the interrupt condition to the actual execution of
the corresponding interrupt task. In particular, it is possible that scheduled
interrupts will not be executed in the preset time, so the program must be
designed to avoid interrupt conflicts if necessary.
Duplicate Processing
in Cyclic and Interrupt
Tasks
If a memory address is processed both by a cyclic task and an interrupt task,
an interrupt mask must be set to disable interrupts.
When an interrupt occurs, execution of the cyclic task will be interrupted
immediately, even during execution of a cyclic task’s instruction, and the par-
tially processed data is saved. After the interrupt task is completed, process-
ing returns to the cyclic task and the interrupted processing restarts with the
data saved before the interrupt processing. If the interrupt task overwrites a
memory address used by one of the interrupted instruction’s operands, that
overwrite may not be reflected after the saved data is restored as processing
returns to the cyclic task.
To prevent an instruction from being interrupted during processing, enter
DI(693) just before the instruction to disable interrupts and EI(694) just after
the instruction to enable interrupts again.
Input interrupt
(direct mode or
counter mode)
>
High-speed
counter inter-
rupt
>
Scheduled
interrupt
Содержание CP1L-EL20DR-D
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Страница 34: ...xxxiv Software Licenses and Copyrights 7...
Страница 178: ...144 Connecting the CX Programmer Section 5 1 Click the Connect button to connect and then connection online is completed...
Страница 192: ...158 Trial Operation and Debugging Section 5 3...
Страница 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Страница 666: ...632 Trouble Shooting Section 11 7...
Страница 696: ...662 Standard Models Appendix A...
Страница 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Страница 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Страница 836: ...802 PLC Setup Appendix G...
Страница 838: ...804 TCP Status Transitions Appendix H...
Страница 840: ...806 Ethernet Network Parameters Appendix I...
Страница 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Страница 844: ...810 Ethernet Specifications Appendix K...
Страница 851: ...Index 817 work words 118 write protection 447...
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