Omron CP1L-EL20DR-D, Руководство по эксплуатации

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788
PLC Setup Appendix G
2 2-2 NT Link (1:N)
2-2-1 Baud 9,600
(disabled) 38,400 (standard) Every cycle 161
(CP1L
EM-type
CPU Unit) 00 to
07 00 hex
115,200 (high speed) 0A hex
2-2-2 NT/PC
Link Max:
Highest
unit num-
ber 0 0 Every cycle 166
(CP1L
EM-type
CPU Unit) 00 to
03 0 hex
: :
7 7 hex
2-3 RS-232C
2-3-1 Baud 9600 bps 300 bps Every cycle 161
(CP1L
EM-type
CPU Unit) 00 to
07 01 hex
600 bps 02 hex
1,200 bps 03 hex
2,400 bps 04 hex
4,800 bps 05 hex
9,600 bps 00 or
06 hex
19,200 bps 07 hex
38,400 bps 08 hex
57,600 bps 09 hex
115,200 bps 0A hex
2-3-2 Format
(data
length,
stop bits,
parity) 7,2,E: 7-bit
data, 2 stop
bits, even parity 7,2,E: 7-bit data, 2 stop
bits, even parity Every cycle 160
(CP1L
EM-type
CPU Unit) 00 to
03 0 hex
7,2,O: 7-bit data, 2 stop
bits, odd parity 1 hex
7,2,N: 7-bit data, 2 stop
bits, no parity 2 hex
7,1,E: 7-bit data, 2 stop
bits, even parity 4 hex
7,1,O: 7-bit data, 1 stop
bit, odd parity 5 hex
7,1,N: 7-bit data, 1 stop
bit, no parity 6 hex
8,2,E: 8-bit data, 2 stop
bits, even parity 8 hex
8,2,O: 8-bit data, 2 stop
bits, odd parity 9 hex
8,2,N: 8-bit data, 2 stop
bits, no parity A hex
8,1,E: 8-bit data, 1 stop
bit, even parity C hex
8,1,O: 8-bit data, 1 stop
bit, odd parity D hex
8,1,N: 8-bit data, 1 stop
bit, no parity E hex
2-3-3 Start Code Disable. Disable. Every cycle 165
(CP1L
EM-type
CPU Unit) 12 0
Set. 1
2-3-4 Start Code 00 hex0x0000 0x0000 Every cycle 164
(CP1L
EM-type
CPU Unit) 08 to
15 00 hex
: :
0x00FF FF hex
2-3-5 End Code Received
Bytes: Receive
specified num-
ber of bytes. Received Bytes: Receive
specified number of
bytes. Every cycle 165
(CP1L
EM-type
CPU Unit) 08 and
09 00
CR,LF 10
Set End Code 01
Name Default Settings When setting is read
by CPU Unit
Internal
address
Bits Settings