NEC V850E/IA1 mPD703116, Руководство пользователя

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CHAPTER 18 ELECTRICAL SPECIFICATIONS
773
User’s Manual U14492EJ3V0UD
(1) Clock timing (1/2)
(T
A
= –40 to
++++
85
°°°°
C:
µµµµ
PD703116, 703116(A), 70F3116, 70F3116(A),
T
A
= –40 to
++++
110
°°°°
C:
µµµµ
PD703116(A1), 70F3116(A1),
V
DD3
= CV
DD
= 3.0 to 3.6 V, V
DD5
= 5 V
±±±±
0.5 V, V
SS3
= V
SS5
= CV
SS
= 0 V,
output pin load capacitance: C
L
= 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Direct mode 31.25 125 ns
PLL mode
Note 1
156 250 ns
Direct mode 20 125 ns
X1 input cycle <1> t
CYX
PLL mode
Note 2
156 250 ns
Direct mode 6 ns X1 input high-level width <2> t
WXH
PLL mode 50 ns
Direct mode 6 ns X1 input low-level width <3> t
WXL
PLL mode 50 ns
Direct mode 4 ns X1 input rise time <4> t
XR
PLL mode 10 ns
Direct mode 4 ns X1 input fall time <5> t
XF
PLL mode 10 ns
Note 2 4 50 MHz
Note 1 4 32 MHz
CPU operation frequency
−
f
XX
CLKOUT signal used
Note 3
4 32 MHz
Note 2 20 250 ns
Note 1 31.25 250 ns
CLKOUT output cycle <6> t
CYK
CLKOUT signal used
Note 3
31.25 250 ns
CLKOUT high-level width <7> t
WKH
0.5T – 9 ns
CLKOUT low-level width <8> t
WKL
0.5T – 11 ns
CLKOUT rise time <9> t
KR
11 ns
CLKOUT fall time <10> t
KF
9 ns
Delay time from X1
↓
to CLKOUT
<11> t
DXK
Direct mode 40 ns
Notes 1. –40°C
≤
T
A
≤
+110°C
2. –40°C
≤
T
A
≤
+85°C
3. When interfacing to the external devices using the CLKOUT signal, make the internal system clock
frequency (f
XX
) 32 MHz or lower.
Remark T = t
CYK