CHAPTER 18 ELECTRICAL SPECIFICATIONS
777
User’s Manual U14492EJ3V0UD
(b)
CLKOUT synchronous (T
A
= –40 to
++++
85
°°°°
C:
µµµµ
PD703116, 703116(A), 70F3116, 70F3116(A),
T
A
= –40 to
++++
110
°°°°
C:
µµµµ
PD703116(A1), 70F3116(A1),
V
DD3
= CV
DD
= 3.0 to 3.6 V, V
DD5
= 5 V
±±±±
0.5 V, V
SS3
= V
SS5
= CV
SS
= 0 V,
output pin load capacitance: C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT
↑
to address
<45>
t
DKA
–7
19
ns
Delay time from CLKOUT
↑
to address float
<46>
t
FKA
–12
15
ns
Delay time from CLKOUT
↓
to ASTB
<47>
t
DKST
–3 + w
AH
T
19 + w
AH
T
ns
Delay time from CLKOUT
↑
to RD, LWR, UWR
<48>
t
DKRDWR
–5
19
ns
Data input setup time (to CLKOUT
↑
)
<49>
t
SIDK
21
ns
Data input hold time (from CLKOUT
↑
)
<50>
t
HKID
5
ns
Delay time from CLKOUT
↑
to data output
<51>
t
DKOD
19
ns
WAIT setup time (to CLKOUT
↓
)
<52>
t
SWTK
21
ns
WAIT hold time (from CLKOUT
↓
)
<53>
t
HKWT
5
ns
HLDRQ setup time (to CLKOUT
↓
)
<54>
t
SHQK
21
ns
HLDRQ hold time (from CLKOUT
↓
)
<55>
t
HKHQ
5
ns
Delay time from CLKOUT
↑
to HLDAK
<56>
t
DKHA
19
ns
Delay time from CLKOUT
↑
to address float
<57>
t
DKF
19
ns
Remarks 1.
T = t
CYK
2.
w
AH
: Number of address hold wait states (0 or 1)
3.
Observe at least either of the data input hold time t
HKID
or
t
HRDID
.
Содержание V850E/IA1 mPD703116
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