NEC V850E/IA1 mPD703116, Руководство пользователя

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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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User’s Manual U14492EJ3V0UD
6.7 Transfer Object
6.7.1 Transfer type and transfer object
Table 6-1 lists the relationships between transfer type and transfer object (
√
: transfer enabled,
×
: transfer disabled).
Table 6-1. Relationship Between Transfer Type and Transfer Object
Destination
Two-Cycle Transfer
Internal ROM On-Chip
Peripheral I/O
Internal RAM External
Memory,
External I/O
On-chip
peripheral I/O
× √ √ √
External I/O
× √ √ √
Internal RAM
× √ × √
External memory
× √ √ √
S
ourc
e
Internal ROM
× × × ×
Cautions 1. The operation is not guaranteed for combinations of transfer destination and source marked
with “
××××
” in Table 6-1.
2. Addresses between 3FFF000H and 3FFFFFFH cannot be specified for the source and
destination address of DMA transfer. Be sure to specify an address between FFFF000H and
FFFFFFFH.
Remark During two-cycle DMA transfer, if the data bus width of the transfer source and that of the transfer
destination are different, the operation becomes as follows.
If the object of the DMA transfer is an on-chip peripheral I/O register (transfer source/transfer
destination), be sure to specify the same transfer size as the register size. For example, in the case of
DMA transfer to an 8-bit register, be sure to specify byte (8-bit) transfer.
<16-bit transfer>
•
Transfer from a 16-bit bus to an 8-bit bus
A read cycle (16 bits) is generated and then a write cycle (8 bits) is generated twice successively.
•
Transfer from an 8-bit bus to a 16-bit bus
A read cycle (8 bits) is generated twice successively and then a write cycle (16 bits) is generated.
<8-bit transfer>
•
Transfer from a 16-bit bus to an 8-bit bus
A read cycle (the higher 8 bits go into a high-impedance state) is generated and then a write cycle (8
bits) is generated.
•
Transfer from an 8-bit bus to a 16-bit bus
A read cycle (8 bits) is generated and then a write cycle (the higher 8 bits go into a high-impedance
state) is generated.