CHAPTER 2 PIN FUNCTIONS
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User’s Manual U14492EJ3V0UD
(7) PCT0 to PCT7 (Port CT) … I/O
Port CT is an 8-bit I/O port in which input or output can be set in 1-bit units.
Besides functioning as a port, in control mode, it operates as control signal output for when memory is
expanded externally.
An operation mode of port or control mode can be selected for each bit and specified by the port CT mode
control register (PMCCT).
(a) Port mode
PCT0 to PCT7 can be set to input or output in 1-bit units using the port CT mode register (PMCT).
(b) Control mode
PCT0 to PCT7 can be set to port or control mode in 1-bit units using PMCCT.
(i) LWR (Lower byte write strobe) … Output
This is a strobe signal that shows that the executing bus cycle is a write cycle for SRAM, external
ROM, or an external peripheral I/O area.
In the data bus, the lower byte is in effect. If the bus cycle is a lower memory write, it becomes
active at the falling edge of a T1 state CLKOUT signal and becomes inactive at the falling edge of a
T2 state CLKOUT signal.
(ii) UWR (Upper byte write strobe) … Output
This is a strobe signal that shows that the executing bus cycle is a write cycle for SRAM, external
ROM, or an external peripheral I/O area.
In the data bus, the upper byte is in effect. If the bus cycle is an upper memory write, it becomes
active at the falling edge of a T1 state CLKOUT signal and becomes inactive at the falling edge of a
T2 state CLKOUT signal.
(iii) RD (Read strobe) … Output
This is a strobe signal that shows that the executing bus cycle is a read cycle for SRAM, external
ROM, or external peripheral I/O. It is inactive in an idle state (TI).
(iv) ASTB (Address strobe) … Output
This is the external address bus latch strobe signal output pin.
Output becomes low level in synchronous with the falling edge of the clock in a T1 state bus cycle,
and high level in synchronous with the falling edge of the clock in a T3 state.
Содержание V850E/IA1 mPD703116
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