NEC V850E/IA1 mPD703116, Руководство пользователя

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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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User’s Manual U14492EJ3V0UD
6.7.2 External bus cycles during DMA transfer (two-cycle transfer)
The external bus cycles during DMA transfer (two-cycle transfer) are shown below.
Table 6-2. External Bus Cycles During DMA Transfer (Two-Cycle Transfer)
Transfer Object External Bus Cycle
On-chip peripheral I/O, internal RAM None
Note
–
External memory, external I/O Yes SRAM, external ROM, external I/O access cycle
Note Other external cycles, such as a CPU-based bus cycle can be started.
6.8 DMA Channel Priorities
The DMA channel priorities are fixed as follows.
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
These priorities are valid in the TI state only. In the block transfer mode, the channel used for transfer is never
switched.
In the single-step transfer mode, if a higher priority DMA transfer request is issued while the bus is released (in the
TI state), the higher priority DMA transfer request is acknowledged.
Caution Do not start more than one DMA channel using the same start factor. If more than one DMA
channel is started, a lower priority DMA channel may be acknowledged prior to a higher priority
DMA channel.
6.9 Next Address Setting Function
The DMA source address registers (DSAnH, DSAnL), DMA destination address registers (DDAnH, DDAnL), and
DMA transfer count register (DBCn) are 2-stage FIFO buffer registers configured with a master register and slave
register (n = 0 to 3).
When the terminal count is issued, these registers are automatically rewritten with the value that was set
immediately before.
Therefore, by making a new DMA transfer setting for these registers during DMA transfer, values will automatically
be updated to the new values after transfer
Note
.
Note If making another new DMA transfer setting, make sure that the current DMA transfer has started first.
Making a new setting before the current DMA transfer starts will overwrite the values of both the master
and slave registers.
Figure 6-8 shows the configuration of the buffer register.