NEC V850E/IA1 mPD703116, Руководство пользователя

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CHAPTER 18 ELECTRICAL SPECIFICATIONS
785
User’s Manual U14492EJ3V0UD
(10) UART1, UART2 timing (1/2)
(a) Clocked master mode
(T
A
= –40 to
++++
85
°°°°
C:
µµµµ
PD703116, 703116(A), 70F3116, 70F3116(A),
T
A
= –40 to
++++
110
°°°°
C:
µµµµ
PD703116(A1), 70F3116(A1),
V
DD3
= CV
DD
= 3.0 to 3.6 V, V
DD5
= 5 V
±±±±
0.5 V, V
SS3
= V
SS5
= CV
SS
= 0 V,
output pin load capacitance: C
L
= 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
ASCKn cycle <73> t
CYSK0
Output 1000 ns
ASCKn high-level width <74> t
WSK0H
Output k T – 20 ns
ASCKn low-level width <75> t
WSK0L
Output k T – 20 ns
RXDn setup time (to ASCKn
↑
)
<76> t
SRXSK
1.5 T + 35 ns
RXDn hold time (from ASCKn
↑
) <77> t
HSKRX
0 ns
TXDn output delay time (from ASCKn
↓
)
<78> t
DSKTX
T + 10 ns
TXDn output hold time (from ASCKn
↑
)
<79> t
HSKTX
(k + 1)T – 20 ns
Remarks 1. T = 2t
CYK
2. k: Setting value of prescaler compare register n (PRSCMn) of UARTn
3. n = 1, 2
(b) Clocked slave mode
(T
A
= –40 to
++++
85
°°°°
C:
µµµµ
PD703116, 703116(A), 70F3116, 70F3116(A),
T
A
= –40 to
++++
110
°°°°
C:
µµµµ
PD703116(A1), 70F3116(A1),
V
DD3
= CV
DD
= 3.0 to 3.6 V, V
DD5
= 5 V
±±±±
0.5 V, V
SS3
= V
SS5
= CV
SS
= 0 V,
output pin load capacitance: C
L
= 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
ASCKn cycle <73> t
CYSK0
Input 1000 ns
ASCKn high-level width <74> t
WSK0H
Input 4 T + 80 ns
ASCKn low-level width <75> t
WSK0L
Input 4 T + 80 ns
RXDn setup time (to ASCKn
↑
) <76> t
SRXSK
T + 10 ns
RXDn hold time (from ASCKn
↑
)
<77> t
HSKRX
T + 10 ns
TXDn output delay time (from ASCKn
↓
)
<78> t
DSKTX
2.5 T + 45 ns
TXDn output hold time (from ASCKn
↑
)
<79> t
HSKTX
k T + 1.5 T ns
Remarks 1. T = 2t
CYK
2. k: Setting value of PRSCMn register of UARTn
3. n = 1, 2