CHAPTER 11 FCAN CONTROLLER
602
User’s Manual U14492EJ3V0UD
Figure 11-27. CAN Main Clock Selection Register (CGCS) Settings
START
f
MEM
f
GTS1
f
GTS
Select clock for memory access controller
(MCP0 to MCP3)
f
MEM
= f
MEM1
/(n + 1)
n = 0 to 15 (set using bits MCP0 to MCP3)
f
GTS
= f
GTS1
/(n + 1)
n = 0 to 255 (set using bits CGTS0 to CGTS7)
GTCS1, GTCS0 = 00: f
GTS1
= f
MEM
/2
GTCS1, GTCS0 = 01: f
GTS1
= f
MEM
/4
GTCS1, GTCS0 = 10: f
GTS1
= f
MEM
/8
GTCS1, GTCS0 = 11: f
GTS1
= f
MEM
/16
Select global timer clock
(GTCS0, GTCS1)
Select system timer prescaler
(CGTS0 to CGTS7)
Remark
f
MEM
= CAN module clock
f
MEM1
= Base clock
f
GTS1
= Global timer clock
f
GTS
= System timer prescaler
Figure 11-28. CAN Global Interrupt Enable Register (CGIE) Settings
START
No
Enable interrupt
for G_IE1 bit
Yes
set G_IE1 = 1
clear G_IE1 = 0
No
Enable interrupt
for G_IE2 bit
• An interrupt occurs if a memory address
in the undefined area is accessed.
• An interrupt occurs if the GOM bit is not
cleared (0) under the following conditions.
• When shutdown is disabled (EFSD bit = 0)
• When a CAN module not in the initialization
status (ISTAT bit = 0) exists
• An interrupt occurs if an illegal write
access is made to the TEMP buffer when
the GOM bit = 1.
• An interrupt occurs if the CAN module
register (register starting with “C1”) is accessed
when the GOM bit = 0.
Yes
set G_IE2 = 1
clear G_IE2 = 0
Remark
GOM: Bit of CAN global status register (CGST)
EFSD: Bit of CAN global status register (CGST)
ISTAT: Bit of CAN1 control register (C1CTRL)
Содержание V850E/IA1 mPD703116
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