CHAPTER 11 FCAN CONTROLLER
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User’s Manual U14492EJ3V0UD
11.9 Cautions on Bit Set/Clear Function
The FCAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN
interface. An operation error occurs if the following registers are written to directly, so do not directly write (via bit
manipulation, read/modify/write, or direct writing of target values) values to them.
• CAN global status register (CGST)
• CAN global interrupt enable register (CGIE)
• CAN1 control register (C1CTRL)
• CAN1 definition register (C1DEF)
• CAN1 interrupt enable register (C1IE)
All 16 bits in the above registers can be read via the usual method. Use the procedure described in Figure 11-23
below to set or clear the lower 8 bits in these registers.
Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (see
Figure 11-24
). Figure 11-23 shows how the values of set bits or clear bits relate to set/clear/no change operations in
the corresponding register.
Figure 11-23. Example of Bit Setting/Clearing Operations
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
0
1
1
1
1
0
1
1
0
0
0
set
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
clear
1
1
0
1
1
0
0
0
Set
Set
No change
No change
Clear
No change
Clear
Clear
Bit status
Register’s current values
Write values
Register’s value after
write operations
Содержание V850E/IA1 mPD703116
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