CHAPTER 14 PORT FUNCTIONS
714
User’s Manual U14492EJ3V0UD
14.4.2 Timer 10, timer 11, timer 3 input pins
Noise filtering using the clock sampling shown below is added to the pins that operate as valid edge inputs to timer
10, timer 11, and timer 3. A signal input that changes in less than these elimination times is not accepted internally.
Pin
Noise Elimination Time
Sampling Clock
Timer 10
P10/TIUD10/TO10
P11/TCUD10/INTP100
P12/TCLR10/INTP101
Timer 11
P13/TIUD11/TO11
P14/TCUD11/INTP110
P15/TCLR11/INTP111
Select from f
XXTM10,11
f
XXTM10,11
/2
f
XXTM10,11
/4
f
XXTM10,11
/8
P26/TI3/INTP30/TCLR3
Select from f
XXTM3
/2
f
XXTM3
/4
f
XXTM3
/8
f
XXTM3
/16
Timer 3
P27/TO3/INTP31
4 to 5 clocks
Select from f
XXTM3
/32
f
XXTM3
/64
f
XXTM3
/128
f
XXTM3
/256
Cautions 1.
Since the above pin noise filtering uses clock sampling, input signals are not received when
the CPU clock is stopped.
2.
The noise eliminator is valid only in control mode.
Remark
f
XXTM10,11
: Clock of TM10 and TM11 selected by PRM02 register
f
XXTM3
:
Clock of TM3 selected by PRM03 register
Содержание V850E/IA1 mPD703116
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