CHAPTER 4 BUS CONTROL FUNCTION
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User’s Manual U14492EJ3V0UD
4.9
Bus Priority Order
There are four external bus cycles: bus hold, DMA cycle, operand data access, and instruction fetch.
In order of priority, bus hold is the highest, followed by DMA cycle, operand data access, and instruction fetch, in
that order.
An instruction fetch may be inserted between a read access and write access during a read modify write access.
Also, an instruction fetch may be inserted between bus accesses when a CPU bus clock is used.
Table 4-1. Bus Priority Order
Priority
Order
External Bus Cycle
Bus Master
High
Bus hold
External device
DMA cycle
DMA controller
Operand data access
CPU
Low
Instruction fetch
CPU
Содержание V850E/IA1 mPD703116
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