6
User’s Manual U14492EJ3V0UD
Major Revisions in This Edition
Page
Description
p.110
Modification of description in
4.2.1 Pin status during internal ROM, internal RAM, and on-chip peripheral
I/O access
p.140
Addition of description to
6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3)
p.140
Addition of description to
6.3.1 (1) DMA source address registers 0H to 3H (DSA0H to DSA3H)
p.142
Addition of description to
6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3)
p.142
Addition of description to
6.3.2 (1) DMA destination address registers 0H to 3H (DDA0H to DDA3H)
p.144
Addition of description to
6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)
p.145
Addition of description and
Caution
to
6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3)
pp.147, 148
Addition of description to and modification and addition of description in
Caution
in
6.3.5 DMA channel
control registers 0 to 3 (DCHC0 to DCHC3)
p.149
Addition and modification of description in
6.3.6 DMA disable status register (DDIS)
p.149
Addition of description to
6.3.7 DMA restart register (DRST)
p.150
Addition of description to
6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
p.158
Modification of description in
Table 6-1 Relationship Between Transfer Type and Transfer Object
p.158
Modification of description in
Remark
in
6.7.1 Transfer type and transfer object
pp.159, 160
Modification and addition of description in
6.9 Next Address Setting Function
p.161
Modification of description in
6.11 Forcible Interruption
p.162
Modification of description in
6.14 (4) Bus arbitration for CPU
p.163
Addition of
6.14 (6) Execution of program and DMA transfer in internal RAM
p.179
Addition of
Caution
to
7.3.4 Interrupt control register (xxICn)
p.183
Addition of
Caution
to
7.3.6 In-service priority register (ISPR)
p.259
Modification of description in
Remark
in
9.1.5 (2) PWM mode 0: Triangular wave modulation (right-left
symmetric waveform control)
p.678
Addition of
Caution
to
14.2 (1) Functions of each port
p.715
Modification of description in
Figure 14-14 Example of Noise Elimination Timing
p.763
Addition of
CHAPTER 18 ELECTRICAL SPECIFICATIONS
p.791
Addition of
CHAPTER 19 PACKAGE DRAWING
p.792
Addition of
CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS
p.793
Addition of
APPENDIX A NOTES ON TARGET SYSTEM DESIGN
p.823
Addition of
APPENDIX E REVISION HISTORY
The mark shows major revised points.
Содержание V850E/IA1 mPD703116
Страница 2: ...2 User s Manual U14492EJ3V0UD MEMO...
