NEC V850E/IA1 mPD703116, Руководство пользователя

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CHAPTER 8 CLOCK GENERATION FUNCTION
208
User’s Manual U14492EJ3V0UD
8.3.4 Clock control register (CKC)
The clock control register is an 8-bit register that controls the internal system clock (f
XX
) in PLL mode. It can be
written to only by a specific sequence combination so that it cannot easily be overwritten by mistake due to erroneous
program execution.
This register can be read/written in 8-bit units.
Caution Do not change bits CKDIV2 to CKDIV0 in direct mode.
7 6 5 4 3 2 1 0 Address Initial value
CKC 0 0 TBCS CESEL 0 CKDIV2 CKDIV1 CKDIV0 FFFFF822H 00H
Bit Position Bit Name Function
5 TBCS Selects the time base counter clock.
0: f
X
/2
8
1: f
X
/2
9
For details, see 8.6.2 Time base counter (TBC) .
4 CESEL Specifies the functions of the X1 and X2 pins.
0: A resonator is connected to the X1 and X2 pins
1: An external clock is connected to the X1 pin
When CESEL = 1, the oscillator feedback loop is disconnected to prevent current
leak in software STOP mode.
Sets the internal system clock frequency (f
XX
) when PLL mode is used.
CKDIV2 CKDIV1 CKDIV0 Internal System Clock (f
XX
)
0 0 0 f
X
0 0 1 2.5 × f
X
0 1 1 5 × f
X
1 1 1 10 × f
X
Other than above Setting prohibited
2 to 0
CKDIV2 to
CKDIV0
Caution When changing the internal system clock during operation,
be sure to set the clock to be changed after setting the
CKDIV2 to CKDIV0 bits to 000 (f
X
).
Example Clock generator settings
CKC Register Operation
Mode
CKSEL Pin
CKDIV2 CKDIV1 CKDIV0
Input Clock (f
X
) Internal System
Clock (f
XX
)
Direct mode High-level input 0 0 0 16 MHz 8 MHz
0 0 0 5 MHz 5 MHz
0 0 1 5 MHz 12.5 MHz
0 1 1 5 MHz 25 MHz
PLL mode Low-level input
1 1 1 5 MHz 50 MHz
Other than above Setting prohibited Setting prohibited