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The pair selection inputs are in simple binary form.
Table XIV
Pair Selection Inputs
SELECTED 17
18
19
20
-> PIN #
∅
OPEN
OPEN
OPEN
OPEN
1
GRD
OPEN
OPEN
OPEN
2
OPEN
GRD
OPEN
OPEN
3
GRD
GRD
OPEN
OPEN
4
OPEN
OPEN
GRD
OPEN
5
GRD
OPEN
GRD
OPEN
6
OPEN
GRD
GRD
OPEN
7
GRD
GRD
GRD
OPEN
8
OPEN
OPEN
OPEN
GRD
9
GRD
OPEN
OPEN
GRD
10
OPEN
GRD
OPEN
GRD
11
GRD
GRD
OPEN
GRD
12
OPEN
OPEN
GRD
GRD
13
GRD
OPEN
GRD
GRD
14
OPEN
GRD
GRD
GRD
15
GRD
GRD
GRD
GRD
For both truth tables "GRD" means ON or Logic 1 and "OPEN" means OFF or Logic
∅
. Both
inputs, (PAIR ENTER) and (EXECUTE), are activated and turned on by connecting them to
ground.
Both outputs (ACKNOWLEDGE) and (ERROR), are the equivalent of open collector NPN
transistors whose emitters are connected to ground. The load for these outputs can be connected
from the +BUS pin (DC voltage source) to the output pin. When the output is ON, current will
flow through the sinking NPN's collector to ground. These transistors can sink a maximum of
.04 amps DC and the +BUS voltage should not be greater than 15 VDC.
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