88
Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 2: Pinout Tables
R
7
IO_L12P_7
AR27
7
IO_L12N_VREF_7
AP27
7
IO_L13P_7
AU33
7
IO_L13N_7
AU32
7
IO_L14P_7
AM27
7
IO_L14N_7
AM26
7
IO_L15P_7
AR33
7
IO_L15N_7
AT33
7
IO_L16P_7
AK27
7
IO_L16N_7
AL26
8
IO_L25P_CC_LC_8
AL13
8
IO_L25N_CC_LC_8
AM13
8
IO_L26P_8
AP11
8
IO_L26N_8
AR11
8
IO_L27P_8
AR14
8
IO_L27N_8
AR13
8
IO_L28P_8
AL11
8
IO_L28N_VREF_8
AM11
8
IO_L29P_8
AT14
8
IO_L29N_8
AT13
8
IO_L30P_8
AP12
8
IO_L30N_8
AR12
8
IO_L31P_8
AU13
8
IO_L31N_8
AU12
8
IO_L32P_8
AK11
8
IO_L32N_8
AJ11
8
IO_L17P_8
AN14
8
IO_L17N_8
AP14
8
IO_L18P_8
AP10
8
IO_L18N_8
AN10
8
IO_L19P_8
AK13
8
IO_L19N_8
AK12
8
IO_L20P_8
AJ10
8
IO_L20N_VREF_8
AJ9
8
IO_L21P_8
AJ12
8
IO_L21N_8
AH12
8
IO_L22P_8
AM10
Table 2-3:
FF1517 Package Pinout (FX140) (Cont’d)
Bank
Pin Description
Pin Number
No Connects
