Xilinx Virtex-4 QV FPGA, Manual

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UG496 (v1.1) June 8, 2012
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Chapter 3
Pinout Diagrams
This chapter provides pinout diagrams for each Virtex-4 QV Radiation-Hardened
package/device combination.
Note:
Multi-function I/O pins are represented in these diagrams by symbols for only one of the pin's
available functions, with precedence given to functionality in the following order:
•
VREF, VRP, or VRN
•
SM1 – SM7
•
ADC1 – ADC7
•
D0 – D31
•
GC
•
CC
•
LC
For example, a pin description such as IO_L25N_CC_SM1_LC_7 is represented with an
SM1-SM7 symbol, a pin description such as IO_L4N_GC_VREF_LC_4 is represented with
a VREF symbol, and a pin description such as IO_L8P_D17_CC_LC_1 is represented with
a D0-D31 symbol.
•
CF1140 Package:
♦
“CF1140 Package Pinout Diagram (SX55),” page 162
♦
“CF1140 Color-Coded SelectIO Interface and Bank Information,” page 163
•
CF1144 Package:
♦
“CF1144 Package Pinout Diagram (FX60),” page 164
♦
“CF1144 Color-Coded SelectIO Interface and Bank Information,” page 165
•
CF1509 Package:
♦
“CF1509 Package Pinout Diagram (LX200),” page 166
♦
“CF1509 Color-Coded SelectIO Interface and Bank Information,” page 167
•
FF1517 Package:
♦
“CF1509 Package Pinout Diagram (FX140),” page 168
♦
“CF1509 Color-Coded SelectIO Interface and Bank Information,” page 169