Xilinx Virtex-4 QV FPGA, Manual

Page: 35 / 180

Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com 35
UG496 (v1.1) June 8, 2012
CF1140 (SX55) Ceramic Flip-Chip Column Grid Package
R
13 IO_L28P_13 Y31 NC
13 IO_L28N_VREF_13 W31 NC
13 IO_L29P_13 AB32 NC
13 IO_L29N_13 AB33 NC
13 IO_L30P_13 AA33 NC
13 IO_L30N_13 AA34 NC
13 IO_L31P_13 AB31 NC
13 IO_L31N_13 AA31 NC
13 IO_L32P_13 Y27 NC
13 IO_L32N_13 Y28 NC
14 IO_L17P_14 V9 NC
14 IO_L17N_14 V8 NC
14 IO_L18P_14 V5 NC
14 IO_L18N_14 V4 NC
14 IO_L19P_14 W6 NC
14 IO_L19N_14 W5 NC
14 IO_L20P_14 W2 NC
14 IO_L20N_VREF_14 W1 NC
14 IO_L21P_14 V12 NC
14 IO_L21N_14 W12 NC
14 IO_L22P_14 W7 NC
14 IO_L22N_14 V7 NC
14 IO_L23P_VRN_14 Y4 NC
14 IO_L23N_VRP_14 W4 NC
14 IO_L24P_CC_LC_14 Y3 NC
14 IO_L24N_CC_LC_14 Y2 NC
14 IO_L1P_14 N4 NC
14 IO_L1N_14 P4 NC
14 IO_L2P_14 N3 NC
14 IO_L2N_14 N2 NC
14 IO_L3P_14 R8 NC
14 IO_L3N_14 T8 NC
14 IO_L4P_14 R7 NC
14 IO_L4N_VREF_14 R6 NC
14 IO_L5P_14 P2 NC
14 IO_L5N_14 P1 NC
Table 2-1: CF1140 Package Pinout (SX55) (Cont’d)
Bank Pin Description
Pin
Number
No Connects