Xilinx Virtex-4 QV FPGA, Manual

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Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com 77
UG496 (v1.1) June 8, 2012
CF1144 (FX60) Ceramic Flip-Chip Column Grid Package
R
N/A VCCINT W12
N/A VCCINT P13
N/A VCCINT T13
N/A VCCINT V13
N/A VCCINT Y13
N/A VCCINT N14
N/A VCCINT R14
N/A VCCINT U14
N/A VCCINT W14
N/A VCCINT AC14
N/A VCCINT M15
N/A VCCINT P15
N/A VCCINT T15
N/A VCCINT V15
N/A VCCINT AB15
N/A VCCINT AD15
N/A VCCINT N16
N/A VCCINT R16
N/A VCCINT W16
N/A VCCINT AC16
N/A VCCINT M17
N/A VCCINT P17
N/A VCCINT V17
N/A VCCINT Y17
N/A VCCINT AB17
N/A VCCINT AD17
N/A VCCINT L18
N/A VCCINT N18
N/A VCCINT R18
N/A VCCINT U18
N/A VCCINT AA18
N/A VCCINT AC18
N/A VCCINT M19
N/A VCCINT T19
N/A VCCINT Y19
N/A VCCINT AB19
N/A VCCINT L20
N/A VCCINT N20
Table 2-2: CF1144 Package(FX60) (Cont’d)
Bank Pin Description
Pin
Number
No Connects