Xilinx Virtex-4 QV FPGA, Manual

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46 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 2: Pinout Tables
R
N/A VCCINT L20
N/A VCCINT U20
N/A VCCINT AA20
N/A VCCINT AC20
N/A VCCINT K21
N/A VCCINT M21
N/A VCCINT T21
N/A VCCINT Y21
N/A VCCINT AB21
N/A VCCINT G22
N/A VCCINT J22
N/A VCCINT L22
N/A VCCINT W22
N/A VCCINT AC22
N/A VCCINT AE22
N/A VCCINT K23
N/A VCCINT M23
N/A VCCINT Y23
N/A VCCINT AD23
N/A VCCINT AF23
N/A VCCINT N24
N/A VCCINT AE24
N/A VCCINT AD25
N/A VCCINT J26
N/A VCCINT N28
N/A VCCINT AE28
Notes:
1. This voltage is also referred to as V
CC_CONFIG
in the Virtex-4 Configuration Guide.
2. Connect this reserved pin to GND.
3. Connect this reserved pin to 2.5V (sharing the same PCB supply distribution as V
CCAUX
is acceptable).
Table 2-1: CF1140 Package Pinout (SX55) (Cont’d)
Bank Pin Description
Pin
Number
No Connects