74
Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 2: Pinout Tables
R
N/A
GND
W13
N/A
GND
AJ13
N/A
GND
M14
N/A
GND
P14
N/A
GND
V14
N/A
GND
AB14
N/A
GND
AM14
N/A
GND
E15
N/A
GND
N15
N/A
GND
R15
N/A
GND
U15
N/A
GND
AC15
N/A
GND
AE15
N/A
GND
H16
N/A
GND
P16
N/A
GND
V16
N/A
GND
Y16
N/A
GND
AH16
N/A
GND
L17
N/A
GND
N17
N/A
GND
U17
N/A
GND
AA17
N/A
GND
AC17
N/A
GND
M18
N/A
GND
P18
N/A
GND
AB18
N/A
GND
AD18
N/A
GND
AM18
N/A
GND
G19
N/A
GND
U19
N/A
GND
AA19
N/A
GND
AG19
N/A
GND
K20
N/A
GND
M20
N/A
GND
V20
N/A
GND
Y20
N/A
GND
AB20
N/A
GND
AK20
Table 2-2:
CF1144 Package(FX60) (Cont’d)
Bank
Pin Description
Pin
Number
No Connects
