Xilinx Virtex-4 QV FPGA, Manual

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162 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 3: Pinout Diagrams
R
CF1140 Package Pinout Diagram (SX55)
X-Ref Target - Figure 3-1
Figure 3-1: CF1140 Ceramic Flip-Chip Column Grid Pinout Diagram (SX55)
C
P D
0 1
2
H
Y U
K
I
O M
W
N
A
B
S
S S
S S
S
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n n
n n n n
n
n
n
n
n
n
n
n
n
n
n
n
n
n n n n n n n
n n n n n n
n n n n n n
n
n
n n
n n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n n n
n n n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
1
2
3
4
5
6
7
8
9
10
11
12
1 3
14
15
16
17
1 8
19
20
21
22
2 3
24
25
26
27
2 8
29
3 0
3 1
3 2
33
3 4
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
1
2
3
4
5
6
7
8
9
10
11
12
1 3
14
15
16
17
1 8
19
20
21
22
2 3
24
25
26
27
2 8
29
3 0
3 1
3 2
33
3 4
CF1140 (XQR4V S X55) − Top View
UG496_C0 3 _01_04020 8
C CCLK
ADC P PROGRAM_B
D DONE
0 1 2
M2, M1, M0
H
Y
U
H S WAPEN
K
TCK
I
TDI
O TDO
M TM
S
W PWRDWN_B
N
D0 - D 3 1
A
B
R R
S VD
GND
VBATT
VCCINT
VCCAUX
S
S M
VCCO
IO_LXXY_#
P_GC
N_GC
CC
VRP
VRN
VREF
U s er I/O Pin s
S M1 - S M7
ADC1 - ADC7
D_IN
C S _B RDWR_B
DOUT_BU S Y
INIT
M u lti-F u nction Pin s :
NO CONNECT
n
Dedicated Pin s Other Pin s
LC
Z
Note s : 1. S M a nd ADC f u nction a lity in m u lti-f u nction us er I/O pin s i s re s erved for f u t u re us e.
2. Dedic a ted S M a nd ADC pin s a re re s erved for f u t u re us e.
J
J
TDP
L
L
TDN