Xilinx Virtex-4 QV FPGA, Manual

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166 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 3: Pinout Diagrams
R
CF1509 Package Pinout Diagram (LX200)
X-Ref Target - Figure 3-5
Figure 3-5: CF1509 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram (LX200)
H
C
N
Y
U
M
S S S
CF1509 (XQR4VLX200) − Top View
UG496_C0 3 _05_04020 8
1
2
3
4
5
6
7
8
9
10
11
12
1 3
14
15
16
17
1 8
19
20
21
22
2 3
24
25
26
27
2 8
29
3 0
3 1
3 2
33
3 4
3 5
3 6
3 7
38
3 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AU
AV
AW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AU
AV
AW
1
2
3
4
5
6
7
8
9
10
11
12
1 3
14
15
16
17
1 8
19
20
21
22
2 3
24
25
26
27
2 8
29
3 0
3 1
3 2
33
3 4
3 5
3 6
3 7
38
3 9
P
B
D
2
W
0
O
K
1
A
I
S S S
C CCLK
ADC
P PROGRAM_B
D DONE
0 1 2
M2, M1, M0
H
Y
U
H S WAPEN
K TCK
I TDI
O TDO
M TM
S
W PWRDWN_B
N
D0 - D 3 1
A
B
R R
S VD
GND
VBATT
VCCINT
VCCAUX
S S
M
VCCO
IO_LXXY_#
P_GC
N_GC
CC
VRP
VRN
VREF
U s er I/O Pin s
S M1 - S M7
ADC1 - ADC7
D_IN
C S _B RDWR_B
DOUT_BU S Y
INIT
M u lti-F u nction Pin s :
NO CONNECT
n
Dedicated Pin s Other Pin s
LC
Z
Z Z Z
Z Z Z
Note s : 1. S M a nd ADC f u nction a lity in m u lti-f u nction us er I/O pin s i s re s erved for f u t u re us e.
2. Dedic a ted S M a nd ADC pin s a re re s erved for f u t u re us e.
J
J
TDP
L
L
TDN