76
Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 2: Pinout Tables
R
N/A
GND
AK30
N/A
GND
C31
N/A
GND
N31
N/A
GND
AC31
N/A
GND
F32
N/A
GND
T32
N/A
GND
AF32
N/A
VCCAUX
AE8
N/A
VCCAUX
V9
N/A
VCCAUX
AB10
N/A
VCCAUX
U11
N/A
VCCAUX
N13
N/A
VCCAUX
T14
N/A
VCCAUX
M16
N/A
VCCAUX
U16
N/A
VCCAUX
AB16
N/A
VCCAUX
AD16
N/A
VCCAUX
L19
N/A
VCCAUX
N19
N/A
VCCAUX
V19
N/A
VCCAUX
AC19
N/A
VCCAUX
W21
N/A
VCCAUX
AB22
N/A
VCCAUX
V24
N/A
VCCAUX
N25
N/A
VCCAUX
U26
N/A
VCCAUX
K27
N/A
VCCINT
AC8
N/A
VCCINT
U10
N/A
VCCINT
W10
N/A
VCCINT
AA10
N/A
VCCINT
V11
N/A
VCCINT
Y11
N/A
VCCINT
N12
N/A
VCCINT
R12
N/A
VCCINT
U12
Table 2-2:
CF1144 Package(FX60) (Cont’d)
Bank
Pin Description
Pin
Number
No Connects