Xilinx Virtex-4 QV FPGA, Manual

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58 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 2: Pinout Tables
R
9 IO_L30P_9 T29
9 IO_L30N_9 T28
9 IO_L31P_9 T26
9 IO_L31N_9 R26
9 IO_L32P_9 U28
9 IO_L32N_9 U27
10 IO_L17P_10 N5
10 IO_L17N_10 N4
10 IO_L18P_10 P5
10 IO_L18N_10 P4
10 IO_L19P_10 P10
10 IO_L19N_10 P9
10 IO_L20P_10 R4
10 IO_L20N_VREF_10 R3
10 IO_L21P_10 T5
10 IO_L21N_10 T4
10 IO_L22P_10 P7
10 IO_L22N_10 P6
10 IO_L23P_VRN_10 P11
10 IO_L23N_VRP_10 R11
10 IO_L24P_CC_LC_10 T6
10 IO_L24N_CC_LC_10 R6
10 IO_L1P_10 L9
10 IO_L1N_10 L8
10 IO_L2P_10 H5
10 IO_L2N_10 H4
10 IO_L3P_10 L10
10 IO_L3N_10 M10
10 IO_L4P_10 M8
10 IO_L4N_VREF_10 M7
10 IO_L5P_10 F5
10 IO_L5N_10 G5
10 IO_L6P_10 G3
10 IO_L6N_10 H3
10 IO_L7P_10 F4
10 IO_L7N_10 F3
Table 2-2: CF1144 Package(FX60) (Cont’d)
Bank Pin Description
Pin
Number
No Connects