10
Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 1: Device Packaging Overview
R
Pin Definitions
provides a description of each pin type listed in Virtex-4 QV FPGA pinout tables.
The "_#" suffix appended to some pin descriptions indicates the bank in which that pin
resides. Pins without this suffix appended are not associated with any particular bank.
Note:
RocketIO
™
transceivers are not supported for Virtex-4 QV FPGAs.
Table 1-2:
Virtex-4 QV FPGA Available I/Os per Device/Package Combination
Virtex-4 QV
Device
User and Differential
I/Os
Virtex-4 QV CF Package
CF1140
CF1144
CF1509
XQR4VSX55
Available User I/Os
640
Differential I/O Pairs
320
XQR4VFX60
Available User I/Os
576
Differential I/O Pairs
288
XQR4VFX140
Available User I/Os
768
Differential I/O Pairs
384
XQR4VLX200
Available User I/Os
960
Differential I/O Pairs
480
Table 1-3:
Virtex-4 QPro FPGA Pin Definitions
Pin Name
Direction
Description
User I/O Pins
IO_LXXY_#
Input/Output
All user I/O pins are capable of differential signalling and can implement
LVDS, LVDSEXT, ULVDS, BLVDS, LVPECL, or LDT pairs. Each user I/O is
labeled “
IO_LXXY_#
”, where:
IO
indicates a user I/O pin.
LXXY
indicates a differential pair, with
XX
a unique pair in the bank and
Y
= [P|N]
for the positive/negative sides of the differential pair.
Multi-Function Pins
IO_LXXY_ZZZ_#
Multi-function pins are labelled “
IO_LXXY_ZZZ_#
”, where
ZZZ
represents
one or more of the functions described below.
For a given multi-function pin, ZZZ is one or more of the following:
ADCn
Input/Output
ADC1 through ADC7 input pins are reserved for future use but can be
used for I/O or other designated functions.
Dn
Input/Output
In SelectMAP mode, D0 through D31 are configuration data pins. These pins
become user I/Os after configuration, unless the SelectMAP port is retained.
CC
(2)
Input/Output
These lower capacitance clock pins connect to Clock Capable I/Os. These
pins do not support LVDS outputs, and they become regular user I/Os
when not needed for clocks.
