Xilinx Virtex-4 QV FPGA, Manual

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Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com 29
UG496 (v1.1) June 8, 2012
CF1140 (SX55) Ceramic Flip-Chip Column Grid Package
R
10 IO_L5P_10 N13
10 IO_L5N_10 N12
10 IO_L6P_10 F4
10 IO_L6N_10 F3
10 IO_L7P_10 C2
10 IO_L7N_10 D2
10 IO_L8P_CC_LC_10 D1
10 IO_L8N_CC_LC_10 E1
10 IO_L9P_CC_LC_10 E3
10 IO_L9N_CC_LC_10 E2
10 IO_L10P_10 J6
10 IO_L10N_10 J5
10 IO_L11P_10 H5
10 IO_L11N_10 H4
10 IO_L12P_10 N10
10 IO_L12N_VREF_10 N9
10 IO_L13P_10 P12
10 IO_L13N_10 P11
10 IO_L14P_10 G3
10 IO_L14N_10 G2
10 IO_L15P_10 L8
10 IO_L15N_10 M8
10 IO_L16P_10 K6
10 IO_L16N_10 L6
10 IO_L25P_CC_LC_10 K3
10 IO_L25N_CC_LC_10 L3
10 IO_L26P_10 K2
10 IO_L26N_10 K1
10 IO_L27P_10 M6
10 IO_L27N_10 M5
10 IO_L28P_10 M3
10 IO_L28N_VREF_10 M2
10 IO_L29P_10 L1
10 IO_L29N_10 M1
10 IO_L30P_10 N5
10 IO_L30N_10 P5
10 IO_L31P_10 P7
10 IO_L31N_10 P6
Table 2-1: CF1140 Package Pinout (SX55) (Cont’d)
Bank Pin Description
Pin
Number
No Connects