Xilinx Virtex-4 QV FPGA, Manual

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12 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 1: Device Packaging Overview
R
TDO_0 Output Boundary-Scan Data Output
TMS_0 Input Boundary-Scan Mode Select
TDP_0, TDN_0 N/A Temperature-sensing diode pins (Anode: TDP, Cathode: TDN).
Reserved Pins
AVDD_SM Input
This pin is reserved and should be connected to 2.5V (sharing the same
PCB supply distribution as V
CCAUX
is acceptable).
AVSS_SM Input This pin is reserved for future use and should be connected to GND.
VN_SM Input This pin is reserved for future use and should be connected to GND.
VP_SM Input This pin is reserved for future use and should be connected to GND.
VREFN_SM Input This pin is reserved for future use and should be connected to GND.
VREFP_SM Input This pin is reserved for future use and should be connected to GND.
AVDD_ADC Input
This pin is reserved and should be connected to 2.5V (sharing the same
PCB supply distribution as V
CCAUX
is acceptable).
AVSS_ADC Input This pin is reserved for future use and should be connected to GND.
VN_ADC Input This pin is reserved for future use and should be connected to GND.
VP_ADC Input This pin is reserved for future use and should be connected to GND.
VREFN_ADC Input This pin is reserved for future use and should be connected to GND.
VREFP_ADC Input This pin is reserved for future use and should be connected to GND.
RSVD N/A Reserved pin —do not connect
Other Pins
GND Input Ground.
V
BATT_#
Input
Decryptor key memory backup supply. If unused, this pin should be tied to
VCC or GND.
V
CCAUX
Input Power-supply pins for auxiliary circuits
V
CCINT
Input Power-supply pins for the internal core logic
V
CCO_#
Input Power-supply pins for the output drivers (per bank)
RocketIO Multi-Gigabit Transceiver (MGT) Pins
AVCCAUXRXA_#,
AVCCAUXRXB_#
Input Analog power supply for receive circuitry of the RocketIO MGT (1.2V).
AVCCAUXTX_# Input Analog power supply for transmit circuitry of the RocketIO MGT (1.2V).
AVCCAUXMGT_# Input Analog power supply for global bias (2.5V).
GNDA_# Input Ground for the analog circuitry of the RocketIO MGT.
MGTCLK_# Input Differential reference clock for the RocketIO MGT.
Table 1-3: Virtex-4 QPro FPGA Pin Definitions (Cont’d)
Pin Name Direction Description