NXP Semiconductors MC9S08LG16, Reference Manual

Page: 90 / 373

Chapter 5 Resets, Interrupts, and General System Control
MC9S08LG32 MCU Series, Rev. 5
90 Freescale Semiconductor
5.8.9 System Clock Gating Control 1Register (SCGC1)
This high-page register contains control bits to enable or disable the bus clock to the TPMx, ADC, IIC,
MTIM, RTC, and SCIx modules. Gating off the clocks to unused peripherals is used to reduce the MCU’s
run and wait currents. See
Section 5.7, “Peripheral Clock Gating ,” for more information.
NOTE
User software must disable the peripheral before disabling the clocks to the
peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers need to be re-initialized by user software.
7 6 5 4 3 2 1 0
R
RTC TPM2 TPM1 ADC MTIM IIC SCI2 SCI1
W
Reset: 0 0 0 0 0 0 0 0
Figure 5-11. System Clock Gating Control 1Register (SCGC1)
Table 5-13. SCGC1 Register Field Descriptions
Field Description
7
RTC
RTC Clock Gate Control — This bit controls the clock gate to the RTC module.
0 Bus clock to the RTC module is disabled.
1 Bus clock to the RTC module is enabled.
6
TPM2
TPM2 Clock Gate Control — This bit controls the clock gate to the TPM2 module.
0 Bus clock to the TPM2 module is disabled.
1 Bus clock to the TPM2 module is enabled.
5
TPM1
TPM1 Clock Gate Control — This bit controls the clock gate to the TPM1 module.
0 Bus clock to the TPM1 module is disabled.
1 Bus clock to the TPM1 module is enabled.
4
ADC
ADC Clock Gate Control — This bit controls the clock gate to the ADC module.
0 Bus clock to the ADC module is disabled.
1 Bus clock to the ADC module is enabled.
3
MTIM
MTIM Clock Gate Control — This bit controls the clock gate to the MTIM module.
0 Bus clock to the MTIM module is disabled.
1 Bus clock to the MTIM module is enabled.
2
IIC
IIC Clock Gate Control — This bit controls the clock gate to the IIC module.
0 Bus clock to the IIC module is disabled.
1 Bus clock to the IIC module is enabled.
1
SCI2
SCI2 Clock Gate Control — This bit controls the clock gate to the SCI2 module.
0 Bus clock to the SCI2 module is disabled.
1 Bus clock to the SCI2 module is enabled.
0
SCI1
SCI1 Clock Gate Control — This bit controls the clock gate to the SCI1 module.
0 Bus clock to the SCI1 module is disabled.
1 Bus clock to the SCI1 module is enabled.