Chapter 10 Inter-Integrated Circuit (S08IICV2)
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor
249
12.3.5
IIC Data I/O Register (IICxD)
Table 12-7. IICxS Field Descriptions
Field
Description
7
TCF
Transfer Complete Flag.
This bit is set on the completion of a byte transfer and should be ignored when address
phase of IIC is going on. This bit is only valid during or immediately following a transfer to the IIC module or from
the IIC module.The TCF bit is cleared by reading the IICxD register in receive mode or writing to the IICxD in
transmit mode.
0 Transfer in progress
1 Transfer complete
6
IAAS
Addressed as a Slave.
The IAAS bit is set when the calling address matches the programmed slave address or
when the GCAEN bit is set and a general call is received. Writing the IICxC register clears this bit.
0 Not addressed
1 Addressed as a slave
5
BUSY
Bus Busy.
The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is set
when a start signal is detected and cleared when a stop signal is detected.
0 Bus is idle
1 Bus is busy
4
ARBL
Arbitration Lost.
This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared
by software by writing a 1 to it.
0 Standard bus operation
1 Loss of arbitration
2
SRW
Slave Read/Write.
When addressed as a slave, the SRW bit indicates the value of the R/W command bit of the
calling address sent to the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave
1
IICIF
IIC Interrupt Flag.
The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by
writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit:
•
One byte transfer completes
•
Match of slave address to calling address
•
Arbitration lost
0 No interrupt pending
1 Interrupt pending
0
RXAK
Receive Acknowledge
. When the RXAK bit is low, it indicates an acknowledge signal has been received after
the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
signal is detected.
0 Acknowledge received
1 No acknowledge received
7
6
5
4
3
2
1
0
R
DATA
W
Reset
0
0
0
0
0
0
0
0
Figure 12-7. IIC Data I/O Register (IICxD)
Summary of Contents for MC9S08LG16
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Page 26: ...Chapter 1 Device Overview MC9S08LG32 MCU Series Rev 5 26 Freescale Semiconductor...
Page 40: ...Chapter 2 Pins and Connections MC9S08LG32 MCU Series Rev 5 40 Freescale Semiconductor...
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