NXP Semiconductors MC9S08LG16, Reference Manual

Page: 111 / 373

Chapter 6 Parallel Input/Output Control
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 111
6.7.4.3 Port D Pull Enable Register (PTDPE)
6.7.4.4 Port D Slew Rate Enable Register (PTDSE)
7 6 5 4 3 2 1 0
R
PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
W
Reset: 0 0 0 0 0 0 0 0
Figure 6-19. Internal Pull Enable for Port D Register (PTDPE)
Table 6-18. PTDPE Register Field Descriptions
Field Description
7:0
PTDPE[7:0]
Internal Pull Enable for Port D Bits — Each of these control bits determines if the internal pullup or pulldown
device is enabled for the associated PTD pin. For Port D pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pullup device disabled for Port D bit n.
1 Internal pullup device enabled for Port D bit n.
7 6 5 4 3 2 1 0
R
PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
W
Reset: 1 1 1 1 1 1 1 1
Figure 6-20. Slew Rate Enable for Port D Register (PTDSE)
Table 6-19. PTDSE Register Field Descriptions
Field Description
7:0
PTDSE[7:0]
Output Slew Rate Enable for Port D Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTD pin. For Port D pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for Port D bit n.
1 Output slew rate control enabled for Port D bit n.